View PIC24HJ32GP202_873554.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2007 microchip technology inc. preliminary ds70289a PIC24HJ32GP202/204 and pic24hj16gp304 data sheet high-performance, 16-bit microcontrollers
ds70289a-page ii preliminary ? 2007 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip tec hnology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are tr ademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2007 microchip technology inc. preliminary ds70289a-page 1 PIC24HJ32GP202/204 and pic24hj16gp304 operating range: ? up to 40 mips operation (@ 3.0-3.6v): - industrial temperature range (-40c to +85c) - extended temperature range (-40c to +125c) high-performance cpu: ? modified harvard architecture ? c compiler optimized instruction set ? 16-bit wide data path ? 24-bit wide instructions ? linear program memory addressing up to 4m instruction words ? linear data memory addressing up to 64 kbytes ? 71 base instructions, mostly 1 word/1 cycle ? sixteen 16-bit general purpose registers ? flexible and powerful addressing modes ? software stack ? 16 x 16 multiply operations ? 32/16 and 16/16 divide operations ? up to 16-bit shifts for up to 40-bit data interrupt controller: ? 5-cycle latency ? 118 interrupt vectors ? up to 21 available interrupt sources ? up to 3 external interrupts ? 7 programmable priority levels ? 4 processor exceptions on-chip flash and sram: ? flash program memory (up to 32 kbytes) ? data sram (2 kbytes) ? boot and general security for program flash digital i/o: ? peripheral pin select functionality ? up to 35 programmable digital i/o pins ? wake-up/interrupt-on-change for up to 21 pins ? output pins can drive from 3.0v to 3.6v ? up to 5v output with open drain configuration ? all digital input pins are 5v tolerant ? 4 ma sink on all i/o pins system management: ? flexible clock options: - external, crystal, resonator, internal rc - fully integrated phase-locked loop (pll) - extremely low jitter pll ? power-up timer ? oscillator start-up timer/stabilizer ? watchdog timer with its own rc oscillator ? fail-safe clock monitor ? reset by multiple sources power management: ? on-chip 2.5v voltage regulator ? switch between clock sources in real time ? idle, sleep and doze modes with fast wake-up timers/capture/compare: ? timer/counters, up to three 16-bit timers: - can pair up to make one 32-bit timer - 1 timer runs as real-time clock with external 32.768 khz oscillator - programmable prescaler ? input capture (up to 4 channels): - capture on up, down or both edges - 16-bit capture input functions - 4-deep fifo on each capture ? output compare (up to 2 channels): - single or dual 16-bit compare mode - 16-bit glitchless pwm mode high-performance, 16- bit microcontrollers
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 2 preliminary ? 2007 microchip technology inc. communication modules: ? 4-wire spi - framing supports i/o interface to simple codecs - supports 8-bit and 16-bit data - supports all serial clock formats and sampling modes ?i 2 c? - full multi-master slave mode support - 7-bit and 10-bit addressing - bus collision detection and arbitration - integrated signal conditioning - slave address masking ?uart - interrupt on address bit detect - interrupt on uart error - wake-up on start bit from sleep mode - 4-character tx and rx fifo buffers - lin bus support -irda ? encoding and decoding in hardware - high-speed baud mode - hardware flow control with cts and rts analog-to-digital converters (adcs): ? 10-bit, 1.1 msps or 12-bit, 500 ksps conversion: - 2 and 4 simultaneous samples (10-bit adc) - up to 13 input channels with auto-scanning - conversion start can be manual or synchronized with 1 of 4 trigger sources - conversion possible in sleep mode - 2 lsb max integral nonlinearity - 1 lsb max differential nonlinearity cmos flash technology: ? low-power, high-speed flash technology ? fully static design ? 3.3v (10%) operating voltage ? industrial and extended temperature ? low-power consumption packaging: ? 28-pin sdip/soic/qfn-s ? 44-pin qfn/tqfp note: see the device variant tables for exact peripheral features per device.
? 2007 microchip technology inc. preliminary ds70289a-page 3 PIC24HJ32GP202/204 and pic24hj16gp304 PIC24HJ32GP202/204 and pic24hj16gp304 product families the device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. table 1: PIC24HJ32GP202/204 and pi c24hj16gp304 controller families device pins program flash memory (kbyte) ram remappable peripherals 10-bit/12-bit adc i 2 c? i/o pins (max) packages remappable pins 16-bit timer input capture output compare std. pwm uart spi PIC24HJ32GP202 28 32 2 16 3 (1) 4 2 1 1 1 adc, 10 ch 1 21 sdip soic qfn-s pic24hj32gp204 44 32 2 26 3 (1) 42111 adc, 13 ch135qfn tqfp pic24hj16gp304 44 16 2 26 3 (1) 4 2 1 1 1 adc, 13 ch 1 35 qfn tqfp note 1: only 2 out of 3 timers are remappable
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 4 preliminary ? 2007 microchip technology inc. pin diagrams pic24hfj32gp202 mclr v ss v dd an0/v ref +/cn2/ra0 an1/v ref -/cn3/ra1 av dd av ss pged1/an2/c2in-/rp0/cn4/rb0 pgec3/ascl1/rp6/cn24/rb6 sosco/t1ck/cn0/ra4 sosci/rp4/cn1/rb4 v ss osco/clko/cn29/ra3 osci/clki/cn30/ra2 v cap /v ddcore int0/rp7/cn23/rb7 tdo/sda1/rp9/cn21/rb9 tck/scl1/rp8/cn22/rb8 an5/rp3/cn7/rb3 an4/rp2/cn6/rb2 pgec1/an3/c2in+/rp1/cn5/rb1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 an9/rp15/cn11/rb15 an10/rp14/cn12/rb14 an11/rp13/cn13/rb13 an12/rp12/cn14/rb12 pged2/tdi/rp10/cn16 / rb10 pgec2/tms/rp11/cn15/rb11 pged3/asda1/rp5/cn27/rb5 28-pin sdip, soic 28-pin qfn-s 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 PIC24HJ32GP202 5 4 mclr v ss v dd an0/v ref +/cn2/ra0 an1/v ref -/cn3/ra1 av dd av ss pged1/an2/c2in-/rp0/cn4/rb0 pgec3/ascl1/rp6/cn24/rb6 sosco/t1ck/cn0/ra4 sosci/rp4/cn1/rb4 vss osco/clko/cn29/ra3 osci/clki/cn30/ra2 v cap /v ddcore int0/rp7/cn23/rb7 tdo/sda1/rp9/cn21/rb9 tck/scl1/rp8/cn22/rb8 an5/rp3/cn7/rb3 an4/rp2/cn6/rb2 pgec1/an3/c2in+/rp1/cn5/rb1 an9/rp15/cn11/rb15 an10/rp14/cn12/rb14 an11/rp13/cn13/rb13 an12/rp12/cn14/rb12 pged2/tdi/rp10/cn16/rb10 pgec2/tms/rp11/cn15/rb11 pged3/asda1/rp5/cn27/rb5
? 2007 microchip technology inc. preliminary ds70289a-page 5 PIC24HJ32GP202/204 and pic24hj16gp304 pin diagrams (continued) 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 scl1/rp8/cn22/rb8 int0/rp7/cn23/rb7 pgec3/ascl1/rp6/cn24/rb6 pged3/asda1/rp5/cn27/rb5 v dd tdi/ra9 sosco/t1ck/cn0/ra4 v ss rp21/cn26/rc5 rp20/cn25/rc4 rp19/cn28/rc3 pgec1/an3/c2in+/rp1/cn5/rb1 pged1/an2/c2in-/rp0/cn4/rb0 an1/v ref -/cn3/ra1 an0/v ref +/cn2/ra0 mclr tms/ra10 av dd av ss an9/rp15/cn11/rb15 an10/rp14/cn12/rb14 an12/rp12/cn14/rb12 pgec2/rp11/cn15/rb11 pged2/rp10/cn16/rb10 v cap /v ddcore v ss rp25/cn19/rc9 rp24/cn20/rc8 rp23/cn17/rc7 rp22/cn18/rc6 sda1/rp9/cn21/rb9 an4/rp2/cn6/rb2 an5/rp3/cn7/rb3 an6/rp16/cn8/rc0 an7/rp17/cn9/rc1 an8/rp18/cn10/rc2 sosci/rp4/cn1/rb4 v dd v ss osci/clki/cn30/ra2 osco/clko/cn29/ra3 tdo/ra8 44-pin tqfp an11/rp13/cn13/rb13 tck/ra7 pic24hj32gp204 pic24hj16gp304
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 6 preliminary ? 2007 microchip technology inc. pin diagrams (continued) 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 scl1/rp8/cn22/rb8 int0/rp7/cn23/rb7 pgec3/ascl1/rp6/cn24/rb6 pged3/asda1/rp5/cn27/rb5 v dd tdi/ra9 sosco/t1ck/cn0/ra4 v ss rp21/cn26/rc5 rp20/cn25/rc4 rp19/cn28/rc3 pgec1/an3/c2in+/rp1/cn5/rb1 pged1/an2/c2in-/rp0/cn4/rb0 an1/v ref -/cn3/ra1 an0/v ref +/cn2/ra0 mclr tms/ra10 av dd av ss an9/rp15/cn11/rb15 an10/rp14/cn12/rb14 an12/rp12/cn14/rb12 pgec2/rp11/cn15/rb11 pged2/rp10/cn16/rb10 v cap /v ddcore v ss rp25/cn19/rc9 rp24/cn20/rc8 rp23/cn17/rc7 rp22/cn18/rc6 sda1/rp9/cn21/rb9 an4/rp2/cn6/rb2 an5/rp3/cn7/rb3 an6/rp16/cn8/rc0 an7/rp17/cn9/rc1 an8/rp18/cn10/rc2 sosci/rp4/cn1/rb4 v dd v ss osci/clki/cn30/ra2 osco/clko/cn29/ra3 tdo/ra8 44-pin tqfp an11/rp13/cn13/rb13 tck/ra7 pic24hj32gp204 pic24hj16gp304
? 2007 microchip technology inc. preliminary ds70289a-page 7 PIC24HJ32GP202/204 and pic24hj16gp304 table of contents 1.0 device overview ............................................................................................................. ............................................................. 9 2.0 cpu......................................................................................................................... ................................................................... 13 3.0 memory organization ......................................................................................................... ........................................................ 19 4.0 flash program memory........................................................................................................ ...................................................... 41 5.0 resets ..................................................................................................................... .................................................................. 47 6.0 interrupt controller ........................................................................................................ ............................................................. 53 7.0 oscillator configuration ....................................... ............................................................. .......................................................... 81 8.0 power-saving features....................................................................................................... ....................................................... 91 9.0 i/o ports ................................................................................................................... .................................................................. 93 10.0 timer1 ..................................................................................................................... ................................................................. 117 11.0 timer2/3 feature........................................................................................................... ........................................................... 119 12.0 input capture.............................................................................................................. .............................................................. 125 13.0 output compare............................................................................................................. .......................................................... 127 14.0 serial peripheral interface (spi).......................................................................................... ..................................................... 133 15.0 inter-integrated circuit (i 2 c) ............................................................................................................................. ........................ 141 16.0 universal asynchronous receiver transmitter (uart) ......................................................................... .................................. 151 17.0 10-bit/12-bit analog-to-digital converter (adc) ............................................................................ ........................................... 159 18.0 special features ........................................................................................................... ........................................................... 173 19.0 instruction set summary .................................................................................................... ...................................................... 181 20.0 development support........................................................................................................ ....................................................... 189 21.0 electrical characteristics ................................................................................................. ......................................................... 193 22.0 packaging information...................................................................................................... ........................................................ 227 appendix a: revision history................................................................................................... .......................................................... 233 index .......................................................................................................................... ....................................................................... 235 the microchip web site ......................................................................................................... ............................................................ 239 customer change notification service ........................................................................................... ................................................... 239 customer support............................................................................................................... ............................................................... 239 reader response ................................................................................................................ .............................................................. 240 product identification system .................................................................................................. .......................................................... 241 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 8 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70289a-page 9 PIC24HJ32GP202/204 and pic24hj16gp304 1.0 device overview this document contains device-specific information for the following devices: ? PIC24HJ32GP202 ? pic24hj32gp204 ? pic24hj16gp304 figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24HJ32GP202/204 and pic24hj16gp304 family of devices. table 1-1 lists the functions of the various pins shown in the pinout diagrams. note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? .
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 10 preliminary ? 2007 microchip technology inc. figure 1-1: PIC24HJ32GP202/204 and pic24hj16gp304 block diagram 16 osc1/clki osc2/clko v dd , v ss timing generation mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset precision reference band gap frc/lprc oscillators regulator voltage v ddcore /v cap uart1 ic1,2,7,8 oc/ spi1 i2c1 porta note: not all pins or features are implement ed on all device pinout configurations. s ee pinout diagrams for the specific pins and features present on each device. pwm1,2 cnx instruction decode & control pch pcl 16 program counter 16-bit alu 23 23 24 23 instruction reg pcu 16 x 16 w register array rom latch 16 ea mux 16 8 interrupt controller psv & table data access control block stack control logic loop control logic address latch program memory data latch address bus literal data 16 16 16 16 data latch address latch 16 x ram data bus 17 x 17 multiplier divide support 16 control signals to various blocks adc1 timers portb remappable address generator units 1-3 pins
? 2007 microchip technology inc. preliminary ds70289a-page 11 PIC24HJ32GP202/204 and pic24hj16gp304 table 1-1: pinout i/o descriptions pin name pin type buffer type description an0-an12 i analog analog input channels. clki clko i o st/cmos ? external clock source input. always associated with osc1 pin function. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with osc2 pin function. osc1 osc2 i i/o st/cmos ? oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. sosci sosco i o st/cmos ? 32.768 khz low-power oscillator crystal input; cmos otherwise. 32.768 khz low-power oscillator crystal output. cn0-cn30 i st change notification inputs. can be software programmed for internal weak pull-ups on all inputs. ic1-ic2 ic7-ic8 i st capture inputs 1/2 capture inputs 7/8 ocfa oc1-oc2 i o st ? compare fault a input (for compare channels 1 and 2). compare outputs 1 through 2. int0 int1 int2 i i i st st st external interrupt 0. external interrupt 1. external interrupt 2. ra0-ra4 ra7-ra15 i/o st porta is a bidirectional i/o port. rb0-rb15 i/o st portb is a bidirectional i/o port. rc0-rc9 i/o st portc is a bidirectional i/o port. t1ck t2ck t3ck i i i st st st timer1 external clock input. timer2 external clock input. timer3 external clock input. u1cts u1rts u1rx u1tx i o i o st ? st ? uart1 clear to send. uart1 ready to send. uart1 receive. uart1 transmit. sck1 sdi1 sdo1 ss1 i/o i o i/o st st ? st synchronous serial clock input/output for spi1. spi1 data in. spi1 data out. spi1 slave synchronization or frame pulse i/o. scl1 sda1 ascl1 asda1 i/o i/o i/o i/o st st st st synchronous serial clock input/output for i2c1. synchronous serial data input/output for i2c1. alternate synchronous serial clock input/output for i2c1. alternate synchronous serial data input/output for i2c1. tms tck tdi tdo i i i o st st st ? jtag test mode select pin. jtag test clock input pin. jtag test data input pin. jtag test data output pin. pgd1/emud1 pgc1/emuc1 pgd2/emud2 pgc2/emuc2 pgd3/emud3 pgc3/emuc3 i/o i i/o i i/o i st st st st st st data i/o pin for programming/debugging communication channel 1. clock input pin for programming/debugging communication channel 1. data i/o pin for programming/debugging communication channel 2. clock input pin for programming/debugging communication channel 2. data i/o pin for programming/debugging communication channel 3. clock input pin for programming/debugging communication channel 3. v ddcore p ? cpu logic filter capacitor connection. v ss p ? ground reference for logic and i/o pins. v ref + i analog analog voltage reference (high) input. v ref - i analog analog voltage reference (low) input. legend: cmos = cmos compatible input or output analog = analog input o = output st = schmitt trigger input with cmos levels i = input p = power
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 12 preliminary ? 2007 microchip technology inc. a vdd p p positive supply for analog modules. mclr i/p st master clear (reset) input. this pin is an active-low reset to the device. a vss p p ground reference for analog modules. v dd p ? positive supply for peripheral logic and i/o pins. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type description legend: cmos = cmos compatible input or output analog = analog input o = output st = schmitt trigger input with cmos levels i = input p = power
? 2007 microchip technology inc. preliminary ds70289a-page 13 PIC24HJ32GP202/204 and pic24hj16gp304 2.0 cpu the PIC24HJ32GP202/204 and pic24hj16gp304 cpu modules have a 16-bit (data) modified harvard architecture with an enhanced instruction set and addressing modes. the cpu has a 24-bit instruction word with a variable length opcode field. the program counter (pc) is 23 bits wide and addresses up to 4m x 24 bits of user program memory space. the actual amount of program memory implemented varies by device. a single-cycle instruction prefetch mechanism is used to help maintain throughput and provides pre- dictable execution. all instructions execute in a single cycle, with the exception of instructions that change the program flow, the double word move ( mov.d ) instruc- tion and the table instructions. overhead-free, single- cycle program loop constructs are supported using the repeat instruction, which is interruptible at any point. the PIC24HJ32GP202/204 and pic24hj16gp304 devices have sixteen, 16-bit working registers in the programmer?s model. each of the working registers can serve as a data, address or address offset register. the 16th working register (w15) operates as a software stack pointer (sp) for interrupts and calls. the PIC24HJ32GP202/204 and pic24hj16gp304 instruction set includes many addressing modes and is designed for optimum c compiler efficiency. for most instructions, the PIC24HJ32GP202/204 and pic24hj16gp304 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. as a result, three parameter instructions can be supported, allowing a + b = c operations to be executed in a single cycle. a block diagram of the cpu is shown in figure 2-1, and the programmer?s model for the PIC24HJ32GP202/ 204 and pic24hj16gp304 is shown in figure 2-2. 2.1 data addressing overview the data space can be linearly addressed as 32k words or 64 kbytes using an address generation unit (agu). the upper 32 kbytes of the data space memory map can optionally be mapped into program space at any 16k program word boundary defined by the 8-bit program space visibility page (psvpag) register. the program to data space mapping feature lets any instruction access program space as if it were data space. the data space also includes 2 kbytes of dma ram, which is primarily used for dma data transfers, but this may be used as general purpose ram. 2.2 special mcu features the PIC24HJ32GP202/204 and pic24hj16gp304 feature a 17-bit by 17-bit, single-cycle multiplier. the multiplier can perform signed, unsigned and mixed- sign multiplication. using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication makes mixed-sign multiplication possible. the PIC24HJ32GP202/204 and pic24hj16gp304 supports 16/16 and 32/16 integer divide operations. all divide instructions are iterative operations. they must be executed within a repeat loop, resulting in a total execution time of 19 instruction cycles. the divide operation can be interrupted during any of those 19 cycles without loss of data. a multi-bit data shifter is used to perform up to a 16-bit, left or right shift in a single cycle. note: this data sheet summarizes the features of this group of PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? .
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 14 preliminary ? 2007 microchip technology inc. figure 2-1: PIC24HJ32GP202/204 and pi c24hj16gp304 cpu core block diagram instruction decode & control pch pcl program counter 16-bit alu 24 23 instruction reg pcu 16 x 16 w register array rom latch ea mux interrupt controller stack control logic loop control logic control signals to various blocks address bus literal data 16 16 16 to peripheral modules data latch address latch 16 x ram address generator units x data bus 17 x 17 divide support 16 16 23 23 16 8 psv & table data access control block 16 16 16 program memory data latch address latch multiplier
? 2007 microchip technology inc. preliminary ds70289a-page 15 PIC24HJ32GP202/204 and pic24hj16gp304 figure 2-2: PIC24HJ32GP202/204 and pic24hj16gp304 programmer?s model pc22 pc0 7 0 d0 d15 program counter data table page address status register working registers w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 w14/frame pointer w15/stack pointer 7 0 program space visibility page address z 0 ? ? ?? rcount 15 0 repeat loop counter ipl2 ipl1 splim stack pointer limit register srl push.s shadow do shadow ? ? 15 0 core configuration register legend corcon ? dc ra n tblpag psvpag ipl0 ov w0/wreg srh c
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 16 preliminary ? 2007 microchip technology inc. 2.3 cpu control registers register 2-1: sr: cpu status register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?dc bit 15 bit 8 r/w-0 (1) r/w-0 (2) r/w-0 (2) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl<2:0> (2) ra n ov z c bit 7 bit 0 legend: c = clear only bit r = readable bit u = unimplemented bit, read as ?0? s = set only bit w = writable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8 dc: mcu alu half carry/borrow bit 1 = a carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred 0 = no carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred bit 7-5 ipl<2:0>: cpu interrupt priority level status bits (2) 111 = cpu interrupt priority level is 7 (15), user interrupts disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) bit 4 ra: repeat loop active bit 1 = repeat loop in progress 0 = repeat loop not in progress bit 3 n: mcu alu negative bit 1 = result was negative 0 = result was non-negative (zero or positive) bit 2 ov: mcu alu overflow bit this bit is used for signed arithmetic (2?s complement). it indicates an overflow of the magnitude which causes the sign bit to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 1 z: mcu alu zero bit 1 = an operation which affects the z bit has set it at some time in the past 0 = the most recent operation which affects the z bit has cleared it (i.e., a non-zero result) bit 0 c: mcu alu carry/borrow bit 1 = a carry-out from the most significant bit (msb) of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: the ipl<2:0> bits are concatenated with the ipl<3> bit (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 2: the ipl<2:0> status bits are read only when nstdis = 1 (intcon1<15>).
? 2007 microchip technology inc. preliminary ds70289a-page 17 PIC24HJ32GP202/204 and pic24hj16gp304 register 2-2: corcon: core control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r/c-0 r/w-0 u-0 u-0 ? ? ? ?ipl3 (1) psv ? ? bit 7 bit 0 legend: c = clear only bit r = readable bit w = writable bit -n = value at por ?1? = bit is set 0? = bit is cleared ?x = bit is unknown u = unimplemented bit, read as ?0? bit 15-4 unimplemented: read as ? 0 ? bit 3 ipl3: cpu interrupt priority level status bit 3 (1) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less bit 2 psv: program space visibility in data space enable bit 1 = program space visible in data space 0 = program space not visible in data space bit 1-0 unimplemented: read as ? 0 ? note 1: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 18 preliminary ? 2007 microchip technology inc. 2.4 arithmetic logic unit (alu) the PIC24HJ32GP202/204 and pic24hj16gp304 arithmetic logic unit (alu) is 16 bits wide and is capa- ble of addition, subtraction, bit shifts and logic opera- tions. unless otherwise mentioned, arithmetic operations are 2?s complement in nature. the alu may affect the values of the carry (c), zero (z), negative (n), overflow (ov) and digit carry (dc) status bits in the sr register depending on the operation. the c and dc status bits operate as borrow and digit borrow bits respectively, for subtraction operations. the alu can perform 8-bit or 16-bit operations depending on the mode of the instruction that is used. data for the alu operation can come from the w reg- ister array, or data memory depending on the address- ing mode of the instruction. likewise, output data from the alu can be written to the w register array or a data memory location. refer to the ?dspic30f/33f programmer?s reference manual? (ds70157) for more information on the sr bits affected by each instruction. the PIC24HJ32GP202/204 and pic24hj16gp304 cpu incorporates hardware support for both multiplica- tion and division. this includes a dedicated hardware multiplier and a support hardware for 16-bit divisor divi- sion. 2.4.1 multiplier using the high-speed 17-bit x 17-bit multiplier, the alu supports unsigned, signed or mixed-sign operation in several multiplication modes: ? 16-bit x 16-bit signed ? 16-bit x 16-bit unsigned ? 16-bit signed x 5-bit (literal) unsigned ? 16-bit unsigned x 16-bit unsigned ? 16-bit unsigned x 5-bit (literal) unsigned ? 16-bit unsigned x 16-bit signed ? 8-bit unsigned x 8-bit unsigned 2.4.2 divider the divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes. 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide the quotient for all divide instructions ends up in w0 and the remainder in w1. a 16-bit signed and unsigned div instructions can specify any w register for both the 16-bit divisor (wn) and any w register (aligned) pair (w(m + 1):wm) for the 32-bit dividend. the divide algo- rithm takes one cycle per bit of divisor, so both 32-bit/ 16-bit and 16-bit/16-bit instructions take the same num- ber of cycles to execute. 2.4.3 multi-bit data shifter the multi-bit data shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. the source can be either a working register or a memory location. the shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. a positive value shifts the operand right. and a negative value shifts the operand left. a value of ? 0 ? does not modify the operand.
? 2007 microchip technology inc. preliminary ds70289a-page 19 PIC24HJ32GP202/204 and pic24hj16gp304 3.0 memory organization the PIC24HJ32GP202/204 and pic24hj16gp304 architecture features separate program and data mem- ory spaces and buses. this architecture also allows the direct access of program memory from the data space during code execution. 3.1 program address space the program address memory space of the PIC24HJ32GP202/204 and pic24hj16gp304 devices is 4m instructions. the space is addressable by a 24-bit value derived either from the 23-bit program counter (pc) during program execution, or from table operation or data space remapping as described in section 3.4 ?interfacing program and data memory spaces? . user application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7fffff). the exception is the use of tblrd/tblwt operations, which use tblpag<7> to permit access to the configuration bits and device id sections of the configuration memory space. the memory maps for the PIC24HJ32GP202/204 and pic24hj16gp304 devices are shown in figure 3-1. figure 3-1: program memory for pic24h j32gp202/204 and pic24hj16gp304 devices note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . reset address 0x000000 0x0000fe 0x000002 0x000100 device configuration user program flash memory 0x005800 0x0057fe (11264 instructions) 0x800000 0xf80000 registers 0xf80017 0xf80018 devid (2) 0xfefffe 0xff0000 0xfffffe 0xf7fffe unimplemented (read ? 0 ?s) goto instruction 0x000004 reserved 0x7ffffe reserved 0x000200 0x0001fe 0x000104 alternate vector table reserved interrupt vector table PIC24HJ32GP202/204 configuration memory space user memory space reset address 0x000000 0x0000fe 0x000002 0x000100 device configuration user program flash memory 0x002c00 0x002bfe (5632 instructions) 0x800000 0xf80000 registers 0xf80017 0xf80018 devid (2) 0xfefffe 0xff0000 0xfffffe 0xf7fffe unimplemented (read ? 0 ?s) goto instruction 0x000004 reserved 0x7ffffe reserved 0x000200 0x0001fe 0x000104 alternate vector table reserved interrupt vector table pic24hj16gp304 configuration memory space user memory space
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 20 preliminary ? 2007 microchip technology inc. 3.1.1 program memory organization the program memory space is organized in word- addressable blocks. although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. the lower word always has an even address, while the upper word has an odd address (see figure 3-2). program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. this arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. 3.1.2 interrupt and trap vectors all PIC24HJ32GP202/204 and pic24hj16gp304 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. a hardware reset vector is provided to redirect code execution from the default value of the pc on device reset to the actual start of code. a goto instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. PIC24HJ32GP202/204 and pic24hj16gp304 devices also have two interrupt vector tables, located from 0x000004 to 0x0000ff and 0x000100 to 0x0001ff. these vector tables allow each of the many device interrupt sources to be handled by separate interrupt service routines (isrs). section 6.1 ?inter- rupt vector table? provides a more detailed discus- sion of the interrupt vector tables. figure 3-2: program memory organization 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?) least significant word most significant word instruction width 0x000001 0x000003 0x000005 0x000007 msw address (lsw address)
? 2007 microchip technology inc. preliminary ds70289a-page 21 PIC24HJ32GP202/204 and pic24hj16gp304 3.2 data address space the PIC24HJ32GP202/204 and pic24hj16gp304 cpu has a separate 16-bit-wide data memory space. the data space is accessed using separate address generation units (agus) for read and write operations. the data memory maps is shown in figure 3-3. all effective addresses (eas) in the data memory space are 16 bits wide and point to the bytes within the data space. this arrangement gives a data space address range of 64 kbytes or 32k words. the lower half of the data memory space (that is, when ea<15> = 0 ) is used for implemented memory addresses, while the upper half (ea<15> = 1 ) is reserved for the program space visibility area (see section 3.4.3 ?reading data from program memory using program space visibility? ). PIC24HJ32GP202/204 and pic24hj16gp304 devices implement up to 30 kbytes of data memory. should an ea point to a location outside of this area, an all-zero word or byte will be returned. 3.2.1 data space width the data memory space is organized in byte address- able, 16-bit wide blocks. data is aligned in data memory and registers as 16-bit words, but all data space eas resolve to bytes. the least significant bytes (lsbs) of each word have even addresses, while the most significant bytes (msbs) have odd addresses. 3.2.2 data memory organization and alignment to maintain backward compatibility with pic ? devices and improve data space memory usage efficiency, the PIC24HJ32GP202/204 and pic24hj16gp304 instruc- tion set supports both word and byte operations. as a consequence of byte accessibility, all effective address calculations are internally scaled to step through word- aligned memory. for example, the core recognizes that post-modified register indirect addressing mode [w s ++] will result in a value of ws + 1 for byte operations and ws + 2 for word operations. data byte reads will read the complete word that contains the byte, using the lsb of any ea to deter- mine which byte to select. the selected byte is placed onto the lsb of the data path. that is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode, but sepa- rate write lines. data byte writes only write to the corre- sponding side of the array or register that matches the byte address. all word accesses must be aligned to an even address. misaligned word data fetches are not supported, so care must be taken when mixing byte and word opera- tions, or when translating from 8-bit mcu code. if a misaligned read or write is attempted, an address error trap is generated. if the error occurred on a read, the instruction underway is completed. if the instruction occurred on a write, the instruction is executed but the write does not occur. in either case, a trap is then exe- cuted, allowing the system and/or user application to examine the machine state prior to execution of the address fault. all byte loads into any w register are loaded into the least significant byte. the most significant byte is not modified. a sign-extend instruction ( se ) is provided to allow users to translate 8-bit signed data to 16-bit signed values. alternatively, for 16-bit unsigned data, user applications can clear the msb of any w register by executing a zero-extend ( ze ) instruction on the appro- priate address. 3.2.3 sfr space the first 2 kbytes of the near data space, from 0x0000 to 0x07ff, is primarily occupied by special function registers (sfrs). these are used by the PIC24HJ32GP202/204 and pic24hj16gp304 core and peripheral modules to control the operation of the device. sfrs are distributed among the modules that they control, and are generally grouped together by module. much of the sfr space contains unused addresses; these are read as ? 0 ?. a complete listing of implemented sfrs, including their addresses, is shown in table 3-1 through table 3-21. 3.2.4 near data space the 8-kbyte area between 0x0000 and 0x1fff is referred to as the near data space. locations in this space are directly addressable via 13-bit absolute address field within all memory direct instructions. additionally, the whole data space is addressable using mov instructions, which support memory direct addressing mode with a 16-bit address field, or by using indirect addressing mode using a working register as an address pointer. note: the actual set of peripheral features and interrupts varies by the device. refer to the corresponding device tables and pinout diagrams for device-specific infor- mation.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 22 preliminary ? 2007 microchip technology inc. figure 3-3: data memory map for PIC24HJ32GP202/204 and pic24hj16gp304 devices with 2 kb ram 0x0000 0x07fe 0x0ffe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x07ff 0xffff optionally mapped into program memory 0x0801 0x0800 0x1000 2 kbyte sfr space 2 kbyte sram space 0x8001 0x8000 sfr space x data ram (x) x data unimplemented (x) 0x0fff 0x1001 0x1fff 0x1ffe 0x2001 0x2000 8 kbyte near data space
? 2007 microchip technology inc. preliminary ds70289a-page 23 PIC24HJ32GP202/204 and pic24hj16gp304 table 3-1: cpu core registers map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets wreg0 0000 working register 0 0000 wreg1 0002 working register 1 0000 wreg2 0004 working register 2 0000 wreg3 0006 working register 3 0000 wreg4 0008 working register 4 0000 wreg5 000a working register 5 0000 wreg6 000c working register 6 0000 wreg7 000e working register 7 0000 wreg8 0010 working register 8 0000 wreg9 0012 working register 9 0000 wreg10 0014 working register 10 0000 wreg11 0016 working register 11 0000 wreg12 0018 working register 12 0000 wreg13 001a working register 13 0000 wreg14 001c working register 14 0000 wreg15 001e working register 15 0800 splim 0020 stack pointer limit register xxxx pcl 002e program counter low word register 0000 pch 0030 ? ? ? ? ? ? ? ? program counter high byte register 0000 tblpag 0032 ? ? ? ? ? ? ? ? table page address pointer register 0000 psvpag 0034 ? ? ? ? ? ? ? ? program memory visibility page address pointer register 0000 rcount 0036 repeat loop counter register xxxx sr 0042 ? ? ? ? ? ? ? dc ipl2 ipl1 ipl0 ra n ov z c 0000 corcon 0044 ? ? ? ? ? ? ? ? ? ? ? ? ipl3 psv ? ? 0000 disicnt 0052 ? ? disable interrupts counter register xxxx legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 24 preliminary ? 2007 microchip technology inc. table 3-2: change notification regi ster map for PIC24HJ32GP202 sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnen1 0060 cn15ie cn14ie cn13ie cn12ie cn11ie ?- ? ? cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0062 ? cn30ie cn29ie ? cn27ie ? ? cn24ie cn23ie cn22ie cn21ie ? ? ? ? cn16ie 0000 cnpu1 0068 cn15pue cn14pue cn13pue cn12pue cn11pue ? ? ? cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 006a ? cn30pue cn29pue ? cn27pue ? ? cn24pue cn23pue cn22pue cn21pue ? ? ? ? cn16pue 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 3-3: change notification register map for pic24hj32gp204 and pic24hj16gp304 sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnen1 0060 cn15ie cn14ie cn13ie cn12ie cn11ie cn10ie cn9ie cn8ie cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0062 ? cn30ie cn29ie cn28ie cn27ie cn26ie cn25ie cn24ie cn23ie cn22ie cn21ie cn20ie cn19ie cn18ie cn17ie cn16ie 0000 cnpu1 0068 cn15pue cn14pue cn13pue cn12pue cn11pue cn10pue cn9pue cn8pue cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 006a ? cn30pue cn29pue cn28pue cn27pue cn26pue cn25pue cn24pue cn23pue cn22pue cn21pue cn20pue cn19pue cn18pue cn17pue cn16pue 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2007 microchip technology inc. preliminary ds70289a-page 25 PIC24HJ32GP202/204 and pic24hj16gp304 table 3-4: interrupt controller register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets intcon1 0080 nstdis ? ? ? ? ? ? ? ? div0err ? matherr addrerr stkerr oscfail ? 0000 intcon2 0082 altivt disi ? ? ? ? ? ? ? ? ? ? ? int2ep int1ep int0ep 0000 ifs0 0084 ? ? ad1if u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if ? t1if oc1if ic1if int0if 0000 ifs1 0086 ? ?int2if ? ? ? ? ? ic8if ic7if ? int1if cnif ? mi2c1if si2c1if 0000 ifs4 008c ? ? ? ? ? ? ? ? ? ? ? ? ? ?u1eif ? 0000 iec0 0094 ? ? ad1ie u1txie u1rxie spi1ie spi1eie t3ie t2ie oc2ie ic2ie ? t1ie oc1ie ic1ie int0ie 0000 iec1 0096 ? ?int2ie ? ? ? ? ? ic8ie ic7ie ? int1ie cnie ? mi2c1ie si2c1ie 0000 iec4 009c ? ? ? ? ? ? ? ? ? ? ? ? ? ?u1eie ? 0000 ipc0 00a4 ? t1ip<2:0> ?oc1ip<2:0> ?ic1ip<2:0> ? int0ip<2:0> 4444 ipc1 00a6 ? t2ip<2:0> ?oc2ip<2:0> ?ic2ip<2:0> ? ? ? ? 4444 ipc2 00a8 ? u1rxip<2:0> ? spi1ip<2:0> ? spi1eip<2:0> ? t3ip<2:0> 4444 ipc3 00aa ? ? ? ? ? ? ? ? ? ad1ip<2:0> ? u1txip<2:0> 4444 ipc4 00ac ? cnip<2:0> ? ? ? ? ? mi2c1ip<2:0> ? si2c1ip<2:0> 4444 ipc5 00ae ? ic8ip<2:0> ?ic7ip<2:0> ? ? ? ? ? int1ip<2:0> 4444 ipc7 00b2 ? ? ? ? ? ? ? ? ? int2ip<2:0> ? ? ? ? 4444 ipc16 00c4 ? ? ? ? ? ? ? ? ? u1eip<2:0> ? ? ? ? 4444 inttreg 00e0 ? ? ? ? ilr<3:0>> ? vecnum<6:0> 4444 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 26 preliminary ? 2007 microchip technology inc. table 3-5: timer register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets tmr1 0100 timer1 register xxxx pr1 0102 period register 1 ffff t1con 0104 ton ? tsidl ? ? ? ? ? ? tgate tckps<1:0> ? tsync tcs ? 0000 tmr2 0106 timer2 register xxxx tmr3hld 0108 timer3 holding register (for 32-bit timer operations only) xxxx tmr3 010a timer3 register xxxx pr2 010c period register 2 ffff pr3 010e period register 3 ffff t2con 0110 ton ? tsidl ? ? ? ? ? ? tgate tckps<1:0> t32 ? tcs ? 0000 t3con 0112 ton ? tsidl ? ? ? ? ? ? tgate tckps<1:0> ? ? tcs ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 3-6: input capture register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ic1buf 0140 input 1 capture register xxxx ic1con 0142 ? ? icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 ic2buf 0144 input 2 capture register xxxx ic2con 0146 ? ? icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 ic7buf 0158 input 7 capture register xxxx ic7con 015a ? ? icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 ic8buf 015c input 8capture register xxxx ic8con 015e ? ? icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 3-7: output compare register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets oc1rs 0180 output compare 1 secondary register xxxx oc1r 0182 output compare 1 register xxxx oc1con 0184 ? ? ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 oc2rs 0186 output compare 2 secondary register xxxx oc2r 0188 output compare 2 register xxxx oc2con 018a ? ? ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2007 microchip technology inc. preliminary ds70289a-page 27 PIC24HJ32GP202/204 and pic24hj16gp304 table 3-8: i2c1 register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets i2c1rcv 0200 ? ? ? ? ? ? ? ? receive register 0000 i2c1trn 0202 ? ? ? ? ? ? ? ?transmit register 00ff i2c1brg 0204 ? ? ? ? ? ? ? baud rate generator register 0000 i2c1con 0206 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c1stat 0208 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 i2c1add 020a ? ? ? ? ? ? address register 0000 i2c1msk 020c ? ? ? ? ? ? address mask register 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 3-9: uart1 register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u1mode 0220 uarten ? usidl iren rtsmd ? uen1 uen0 wake lpback abaud urxinv brgh pdsel<1:0> stsel 0000 u1sta 0222 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 u1txreg 0224 ? ? ? ? ? ? ? uart transmit register xxxx u1rxreg 0226 ? ? ? ? ? ? ? uart receive register 0000 u1brg 0228 baud rate generator prescaler 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 3-10: spi1 register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets spi1stat 0240 spien ? spisidl ? ? ? ? ? ? spirov ? ? ? ? spitbf spirbf 0000 spi1con1 0242 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre<2:0> ppre<1:0> 0000 spi1con2 0244 frmen spifsd frmpol ? ? ? ? ? ? ? ? ? ? ? frmdly ? 0000 spi1buf 0248 spi1 transmit and receive buffer register 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 28 preliminary ? 2007 microchip technology inc. table 3-11: peripheral pin select input register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpinr0 0680 ? ? ? int1r<4:0> ? ? ? ? ? ? ? ? 1f00 rpinr1 0682 ? ? ? ? ? ? ? ? ? ? ?int2r<4:0> 001f rpinr3 0686 ? ? ?t3ckr<4:0> ? ? ?t2ckr<4:0> 1f1f rpinr7 068e ? ? ? ic2r<4:0> ? ? ? ic1r<4:0> 1f1f rpinr10 0694 ? ? ? ic8r<4:0> ? ? ? ic7r<4:0> 1f1f rpinr11 0696 ? ? ? ? ? ? ? ? ? ? ?ocfar<4:0> 001f rpinr18 06a4 ? ? ? u1ctsr<4:0> ? ? ?u1rx 1f1f rpinr20 06a8 ? ? ?sck1r<4:0> ? ? ?sdi1r<4:0> 1f1f rpinr21 06aa ? ? ? ? ? ? ? ? ? ? ?ss1r<4:0> 001f legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 3-12: peripheral pin select outp ut register map for PIC24HJ32GP202 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06c0 ? ? ? rp1r<4:0> ? ? ? rp0r<4:0> 0000 rpor1 06c2 ? ? ?rp3r<4:0> ? ? ? rp2r<4:0> 0000 rpor2 06c4 ? ? ?rp5r<4:0> ? ? ? rp4r<4:0> 0000 rpor3 06c6 ? ? ?rp7r<4:0> ? ? ? rp6r<4:0> 0000 rpor4 06c8 ? ? ?rp9r<4:0> ? ? ? rp8r<4:0> 0000 rpor5 06ca ? ? ?rp11r<4:0> ? ? ?rp10r<4:0> 0000 rpor6 06cc ? ? ?rp13r<4:0> ? ? ?rp12r<4:0> 0000 rpor7 06ce ? ? ?rp15r<4:0> ? ? ?rp14r<4:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2007 microchip technology inc. preliminary ds70289a-page 29 PIC24HJ32GP202/204 and pic24hj16gp304 table 3-13: peripheral pin select output regi ster map for pic24hj32gp204 and pic24hj16gp304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06c0 ? ? ? rp1r<4:0> ? ? ? rp0r<4:0> 0000 rpor1 06c2 ? ? ?rp3r<4:0> ? ? ? rp2r<4:0> 0000 rpor2 06c4 ? ? ?rp5r<4:0> ? ? ? rp4r<4:0> 0000 rpor3 06c6 ? ? ?rp7r<4:0> ? ? ? rp6r<4:0> 0000 rpor4 06c8 ? ? ?rp9r<4:0> ? ? ? rp8r<4:0> 0000 rpor5 06ca ? ? ?rp11r<4:0> ? ? ?rp10r<4:0> 0000 rpor6 06cc ? ? ?rp13r<4:0> ? ? ?rp12r<4:0> 0000 rpor7 06ce ? ? ?rp15r<4:0> ? ? ?rp14r<4:0> 0000 rpor8 06d0 ? ? ? rp17r<4:0> ? ? ?rp16r<4:0> 0000 rpor9 06d2 ? ? ? rp19r<4:0> ? ? ?rp18r<4:0> 0000 rpor10 06d4 ? ? ?rp21r<4:0> ? ? ?rp20r<4:0> 0000 rpor11 06d6 ? ? ?rp23r<4:0> ? ? ?rp22r<4:0> 0000 rpor12 06d8 ? ? ?rp25r<4:0> ? ? ?rp24r<4:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 30 preliminary ? 2007 microchip technology inc. table 3-14: adc1 register map for pic24hj32gp204 and pic24hj16gp304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adc1buf0 0300 adc data buffer 0 xxxx adc1buf1 0302 adc data buffer 1 xxxx adc1buf2 0304 adc data buffer 2 xxxx adc1buf3 0306 adc data buffer 3 xxxx adc1buf4 0308 adc data buffer 4 xxxx adc1buf5 030a adc data buffer 5 xxxx adc1buf6 030c adc data buffer 6 xxxx adc1buf7 030e adc data buffer 7 xxxx adc1buf8 0310 adc data buffer 8 xxxx adc1buf9 0312 adc data buffer 9 xxxx adc1bufa 0314 adc data buffer 10 xxxx adc1bufb 0316 adc data buffer 11 xxxx adc1bufc 0318 adc data buffer 12 xxxx adc1bufd 031a adc data buffer 13 xxxx adc1bufe 031c adc data buffer 14 xxxx adc1bufe 031e adc data buffer 15 xxxx ad1con1 0320 adon ?adsidl ? ? ad12b form<1:0> ssrc<2:0> ? simsam asam samp done 0000 ad1con2 0322 vcfg<2:0> ? ? cscna chps<1:0> bufs ? smpi<3:0> bufm alts 0000 ad1con3 0324 adrc ? ? samc<4:0> adcs<7:0> 0000 ad1chs123 0326 ? ? ? ? ? ch123nb<1:0> ch123sb ? ? ? ? ? ch123na<1:0> ch123sa 0000 ad1chs0 0328 ch0nb ? ? ch0sb<4:0> ch0na ? ? ch0sa<4:0> 0000 ad1pcfgl 032c ? ? ? pcfg12 pcfg11 pcfg10 pcfg9 pcfg8 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 ad1cssl 0330 ? ? ? css12 css11 css10 css9 css8 css7 css6 css5 css4 css3 css2 css1 css0 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2007 microchip technology inc. preliminary ds70289a-page 31 PIC24HJ32GP202/204 and pic24hj16gp304 table 3-15: adc1 register map for PIC24HJ32GP202 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 b it 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adc1buf0 0300 adc data buffer 0 xxxx adc1buf1 0302 adc data buffer 1 xxxx adc1buf2 0304 adc data buffer 2 xxxx adc1buf3 0306 adc data buffer 3 xxxx adc1buf4 0308 adc data buffer 4 xxxx adc1buf5 030a adc data buffer 5 xxxx adc1buf6 030c adc data buffer 6 xxxx adc1buf7 030e adc data buffer 7 xxxx adc1buf8 0310 adc data buffer 8 xxxx adc1buf9 0312 adc data buffer 9 xxxx adc1bufa 0314 adc data buffer 10 xxxx adc1bufb 0316 adc data buffer 11 xxxx adc1bufc 0318 adc data buffer 12 xxxx adc1bufd 031a adc data buffer 13 xxxx adc1bufe 031c adc data buffer 14 xxxx adc1buff 031e adc data buffer 15 xxxx ad1con1 0320 adon ?adsidl ? ? ad12b form<1:0> ssrc<2:0> ? simsam asam samp done 0000 ad1con2 0322 vcfg<2:0> ? ? cscna chps<1:0> bufs ? smpi<3:0> bufm alts 0000 ad1con3 0324 adrc ? ? samc<4:0> adcs<7:0> 0000 ad1chs123 0326 ? ? ? ? ? ch123nb<1:0> ch123sb ? ? ? ? ? ch123na<1:0> ch123sa 0000 ad1chs0 0328 ch0nb ? ? ch0sb<4:0> ch0na ? ? ch0sa<4:0> 0000 ad1pcfgl 032c ? ? ? pcfg12 pcfg11 pcfg10 pcfg9 ? ? ? pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 ad1cssl 0330 ? ? ? css12 css11 css10 css9 ? ? ? css5 css4 css3 css2 css1 css0 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 32 preliminary ? 2007 microchip technology inc. table 3-16: porta register map for PIC24HJ32GP202 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 02c0 ? ? ? ? ? ? ? ? ? ? ? trisa4 trisa3 trisa2 trisa1 trisa0 001f porta 02c2 ? ? ? ? ? ? ? ? ? ? ? ra4 ra3 ra2 ra1 ra0 xxxx lata 02c4 ? ? ? ? ? ? ? ? ? ? ? lata4 lata3 lata2 lata1 lata0 xxxx odca 02c6 ? ? ? ? ? ? ? ? ? ? ? odca4 odca3 odca2 odca1 odca0 xxxx legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 3-17: porta register map for pic24hj32gp204 and pic24hj16gp304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 02c0 ? ? ? ? ? trisa10 trisa9 trisa8 trisa7 ? ? trisa4 trisa3 trisa2 trisa1 trisa0 079f porta 02c2 ? ? ? ? ? ra10 ra9 ra8 ra7 ? ? ra4 ra3 ra2 ra1 ra0 xxxx lata 02c4 ? ? ? ? ? lata10 lata9 lata8 lata7 ? ? lata4 lata3 lata2 lata1 lata0 xxxx odca 02c6 ? ? ? ? ? odca10 odca9 odca8 odca7 ? ? odca4 odca3 odca2 odca1 odca0 xxxx legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 3-18: portb register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb15 trisb14 trisb13 trisb12 trisb11 trisb10 trisb9 trisb8 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 ffff portb 02ca rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx latb 02cc latb15 latb14 latb13 latb12 latb11 latb10 latb9 latb8 latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx odcb 02ce odcb15 odcb14 odcb13 odcb12 odcb11 odcb10 odcb9 odcb8 odcb7 odcb6 odcb5 odcb4 odcb3 odcb2 odcb1 odcb0 xxxx legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal for pinhigh devices. table 3-19: portc register map for pic24hj32gp204 and pic24hj16gp304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisc 02d0 ? ? ? ? ? ? trisc9 trisc8 trisc7 trisc6 trisc5 t risc4 trisc3 trisc2 trisc1 trisc0 03ff portc 02d2 ? ? ? ? ? ? rc9 rc8 rc7 rc6 rc5 rc4 rc4 rc2 rc1 rc0 xxxx latc 02d4 ? ? ? ? ? ? latc9 latc8 latc7 latc6 latc5 latc4 latc4 latc2 latc1 latc0 xxxx odcc 02d6 ? ? ? ? ? ? odcc9 odcc8 odcc7 odcc6 odcc5 odcc4 odcc4 odcc2 odcc1 odcc0 xxxx legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2007 microchip technology inc. preliminary ds70289a-page 33 PIC24HJ32GP202/204 and pic24hj16gp304 table 3-20: nvm register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0760 wr wren wrerr ? ? ? ? ? ? erase ? ?nvmop<3:0> 0000 (1) nvmkey 0766 ? ? ? ? ? ? ? ? nvmkey<7:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: reset value shown is for por only. value on other reset states is dependent on the state of memory write or erase operations at the time of reset. table 3-21: pmd register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0770 ? ? t3md t2md t1md ? ? ? i2c1md ? u1md ? spi1md ? ? ad1md 0000 pmd2 0772 ic8md ic7md ? ? ? ?ic2mdic1md ? ? ? ? ? ?oc2mdoc1md 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 34 preliminary ? 2007 microchip technology inc. 3.2.5 software stack in addition to its use as a working register, the w15 register in the PIC24HJ32GP202/204 and pic24hj16gp304 devices is also used as a software stack pointer. the stack pointer always points to the first available free word and grows from lower to higher addresses. it pre-decrements for stack pops and post- increments for stack pushes, as shown in figure 3-4. for a pc push during any call instruction, the msb of the pc is zero-extended before the push, ensuring that the msb is always clear. the stack pointer limit register (splim) associated with the stack pointer sets an upper address boundary for the stack. splim is uninitialized at reset. similarly, the stack pointer, splim<0> is forced to ? 0 ? because all stack operations must be word aligned. when an ea is generated using w15 as a source or destination pointer, the resulting address is compared with the value in splim. if the contents of the stack pointer (w15) and the splim register are equal and a push operation is performed, a stack error trap will not occur. the stack error trap will occur on a subsequent push operation. for example, to cause a stack error trap when the stack grows beyond address 0x2000 in ram, initialize the splim with the value 0x1ffe. similarly, a stack pointer underflow (stack error) trap is generated when the stack pointer address is found to be lesser than 0x0800. this prevents the stack from interfering with the special function register (sfr) space. a write to the splim register should not be immediately followed by an indirect read operation using w15. figure 3-4: call stack frame 3.2.6 data ram protection feature the pic24h product family supports data ram protection features that enable segments of ram to be protected when used in conjunction with boot and secure code segment security. bsram (secure ram segment for bs) is accessible only from the boot segment flash code when enabled. ssram (secure ram segment for ram) is accessible only from the secure segment flash code when enabled. see table 3-1 for an overview of the bsram and ssram sfrs. 3.3 instruction addressing modes the addressing modes shown in table 3-22 form the basis of the addressing modes optimized to support the specific features of individual instructions. the addressing modes provided in the mac class of instruc- tions differ from those in the other instruction types. 3.3.1 file register instructions most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). most file register instructions employ a working register, w0, which is denoted as wreg in these instructions. the destination is typically either the same file register or wreg (with the exception of the mul instruction), which writes the result to a register or register pair. the mov instruction allows additional flexibility and can access the entire data space. 3.3.2 mcu instructions the three-operand mcu instructions are of the form: operand 3 = operand 1 operand 2 where, operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as wb. operand 2 can be a w register, fetched from data memory, or a 5-bit literal. the result location can be either a w register or a data memory location. the following addressing modes are supported by mcu instructions: ? register direct ? register indirect ? register indirect post-modified ? register indirect pre-modified ? 5-bit or 10-bit literal note: a pc push during exception processing concatenates the srl register to the msb of the pc prior to the push. pc<15:0> 000000000 0 15 w15 (before call ) w15 (after call ) stack grows toward higher address 0x0000 pc<22:16> pop : [--w15] push : [w15++] note: not all instructions support all the addressing modes given above. individual instructions can support different subsets of these addressing modes.
? 2007 microchip technology inc. preliminary ds70289a-page 35 PIC24HJ32GP202/204 and pic24hj16gp304 table 3-22: fundamental addressing modes supported 3.3.3 move ( mov ) instruction move instructions provide a greater degree of address- ing flexibility than the other instructions. in addition to the addressing modes supported by most mcu instructions, mov instructions also support register indirect with register offset addressing mode. this is also referred to as register indexed mode. in summary, move instructions support the following addressing modes: ? register direct ? register indirect ? register indirect post-modified ? register indirect pre-modified ? register indirect with register offset (indexed) ? register indirect with literal offset ? 8-bit literal ? 16-bit literal 3.3.4 other instructions besides the addressing modes outlined previously, some instructions use literal constants of various sizes. for example, bra (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the disi instruction uses a 14-bit unsigned literal field. in some instructions, such as add acc , the source of an operand or result is implied by the opcode itself. certain operations, such as nop , do not have any operands. addressing mode description file register direct the address of the file register is specified explicitly. register direct the contents of a register are accessed directly. register indirect the contents of wn forms the effective address (ea.) register indirect post-modified the contents of wn forms the ea. wn is post-modified (incremented or decremented) by a constant value. register indirect pre-modified wn is pre-modified (incremented or decremented) by a signed constant value to form the ea. register indirect with register offset (register indexed) the sum of wn and wb forms the ea. register indirect with literal offset the sum of wn and a literal forms the ea. note: for the mov instructions, the addressing mode specified in the instruction can differ for the source and the destination ea. however, the 4-bit wb (register offset) field is shared by both source and destination (but typically only used by one). note: not all instructions support all the address- ing modes given above. individual instruc- tions may support different subsets of these addressing modes.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 36 preliminary ? 2007 microchip technology inc. 3.4 interfacing program and data memory spaces the PIC24HJ32GP202/204 and pic24hj16gp304 architecture uses a 24-bit-wide program space and a 16-bit wide data space. the architecture is also a mod- ified harvard scheme, which means that the data can also be present in the program space. to use this data successfully, it must be accessed in a way that pre- serves the alignment of information in both spaces. aside from normal execution, the PIC24HJ32GP202/ 204 and pic24hj16gp304 architecture provides two methods by which program space can be accessed during operation: ? using table instructions to access individual bytes or words anywhere in the program space ? remapping a portion of the program space into the data space (program space visibility) table instructions allow an application to read or write to small areas of the program memory. this capability makes the method ideal for accessing data tables that need to be updated periodically. it also allows access to all bytes of the program word. the remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. the application can only access the least significant word of the program word. 3.4.1 addressing program space since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. the solution depends on the interface method to be used. for table operations, the 8-bit table page register (tblpag) is used to define a 32k word region within the program space. this is concatenated with a 16-bit ea to arrive at a full 24-bit program space address. in this format, the most significant bit of tblpag is used to determine if the operation occurs in the user memory (tblpag<7> = 0 ) or the configuration memory (tblpag<7> = 1 ). for remapping operations, the 8-bit program space visibility register (psvpag) is used to define a 16k word page in the program space. when the most significant bit of the ea is ? 1 ?, psvpag is concatenated with the lower 15 bits of the ea to form a 23-bit program space address. unlike table operations, this limits remapping operations strictly to the user memory area. table 3-23 and figure 3-5 show how the program ea is created for table operations and remapping accesses from the data ea. here, p<23:0> refers to a program space word, and d<15:0> refers to a data space word. table 3-23: program space address construction access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access (code execution) user 0 pc<22:1> 0 0xx xxxx xxxx xxxx xxxx xxx0 tblrd/tblwt (byte/word read/write) user tblpag<7:0> data ea<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx configuration tblpag<7:0> data ea<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx program space visibility (block remap/read) user 0 psvpag<7:0> data ea<14:0> (1) 0 xxxx xxxx xxx xxxx xxxx xxxx note 1: data ea<15> is always ? 1 ? in this case, but is not used in calculating the program space address. bit 15 of the address is psvpag<0>.
? 2007 microchip technology inc. preliminary ds70289a-page 37 PIC24HJ32GP202/204 and pic24hj16gp304 figure 3-5: data access from program space address generation 0 program counter 23 bits 1 psvpag 8 bits ea 15 bits program counter (1) select tblpag 8 bits ea 16 bits byte select 0 0 1/0 user/configuration table operations (2) program space visibility (1) space select 24 bits 23 bits (remapping) 1/0 0 note 1: the least significant bit (lsb) of program space addresses is always fixed as ? 0 ? to maintain word alignment of data in the program and data spaces. 2: table operations are not required to be word-aligned. table read operations are permitted in the configuration memory space.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 38 preliminary ? 2007 microchip technology inc. 3.4.2 data access from program memory using table instructions the tblrdl and tblwtl instructions offer a direct method to read or write the lower word of any address within the program space without going through data space. the tblrdh and tblwth instructions are the only methods to read or write the upper 8 bits of a pro- gram space word as data. the pc is incremented by 2 for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. program memory can thus be regarded as two 16-bit wide word address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space that contains the least significant data word. tblrdh and tblwth access the space that contains the upper data byte. two table instructions are provided to move byte or word sized (16-bit) data to and from program space. both function as either byte or word operations. ? tblrdl (table read low): in word mode, this instruction maps the lower word of the program space location (p<15:0>) to a data address (d<15:0>). in byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. the upper byte is selected when byte select is ? 1 ?; the lower byte is selected when it is ? 0 ?. ? tblrdh ( table read high): in word mode, this instruction maps the entire upper word of a program address (p<23:16>) to a data address. note that d<15:8>, the ?phantom byte?, will always be ? 0 ?. in byte mode, this instruction maps the upper or lower byte of the program word to d<7:0> of the data address, as in the tblrdl instruction. note that the data will always be ? 0 ? when the upper ?phantom? byte is selected (byte select = 1 ). in a similar fashion, two table instructions, tblwth and tblwtl , are used to write individual bytes or words to a program space address. the details of their operation are explained in section 4.0 ?flash program memory? . for all table operations, the area of program memory space to be accessed is determined by the table page register (tblpag). tblpag covers the entire program memory space of the device, including user and config- uration spaces. when tblpag<7> = 0 , the table page is located in the user memory space. when tblpag<7> = 1 , the page is located in configuration space. figure 3-6: accessing program memory with table instructions 0 8 16 23 00000000 00000000 00000000 00000000 ?phantom? byte tblrdh.b (wn<0> = 0 ) tblrdl.w tblrdl.b (wn<0> = 1 ) tblrdl.b (wn<0> = 0 ) 23 15 0 tblpag 02 0x000000 0x800000 0x020000 0x030000 program space the address for the table operation is determined by the data ea within the page defined by the tblpag register. only read operations are shown; write operations are also valid in the user memory area.
? 2007 microchip technology inc. preliminary ds70289a-page 39 PIC24HJ32GP202/204 and pic24hj16gp304 3.4.3 reading data from program memory using program space visibility the upper 32 kbytes of data space may optionally be mapped into any 16k word page of the program space. this option provides transparent access to the stored constant data from the data space without the need to use special instructions (such as tblrdl/h ). program space access through the data space occurs if the most significant bit of the data space ea is ? 1 ? and program space visibility is enabled by setting the psv bit in the core control register (corcon<2>). the location of the program memory space to be mapped into the data space is determined by the program space visibility page register (psvpag). this 8-bit register defines any one of 256 possible pages of 16k words in program space. in effect, psvpag functions as the upper 8 bits of the program memory address, with the 15 bits of the ea functioning as the lower bits. by incrementing the pc by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the cor- responding program space addresses. data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. although each data space address 8000h and higher maps directly into a corresponding program memory address (see figure 3-7), only the lower 16 bits of the 24-bit program word are used to contain the data. the upper 8 bits of any program space location used as data should be programmed with ? 1111 1111 ? or ? 0000 0000 ? to force a nop . this prevents possible issues should the area of code ever be accidentally executed. for operations that use psv and are executed outside a repeat loop, the mov and mov.d instructions require one instruction cycle in addition to the specified execution time. all other instructions require two instruction cycles in addition to the specified execution time. for operations that use psv, and are executed inside a repeat loop, these instances require two instruc- tion cycles in addition to the specified execution time of the instruction: ? execution in the first iteration ? execution in the last iteration ? execution prior to exiting the loop due to an interrupt ? execution upon re-entering the loop after an interrupt is serviced any other iteration of the repeat loop will allow the instruction using psv to access data to execute in a single cycle. figure 3-7: program spac e visibility operation note: psv access is temporarily disabled during table reads/writes. 23 15 0 psvpag data space program space 0x0000 0x8000 0xffff 02 0x000000 0x800000 0x010000 0x018000 when corcon<2> = 1 and ea<15> = 1 : the data in the page designated by psvpag is mapped into the upper half of the data memory space... data ea<14:0> ...while the lower 15 bits of the ea specify an exact address within the psv area. this corresponds exactly to the same lower 15 bits of the actual program space address. psv area
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 40 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70289a-page 41 PIC24HJ32GP202/204 and pic24hj16gp304 4.0 flash program memory the PIC24HJ32GP202/204 and pic24hj16gp304 devices contain internal flash program memory to store and execute application code. the memory is readable, writable and erasable during normal opera- tion over the entire v dd range. flash memory can be programmed in two ways: ? in-circuit serial programming? (icsp?) programming capability ? run-time self-programming (rtsp) icsp allows a PIC24HJ32GP202/204 and pic24hj16gp304 device to be serially programmed while in the end application circuit. this is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: pgc1/ pgd1, pgc2/pgd2 or pgc3/pgd3), and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firm- ware to be programmed. rtsp is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user application can write program memory data either in ?blocks? or ?rows? of 64 instructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or ?pages? of 512 instructions (1536 bytes) at a time. 4.1 table instructions and flash programming regardless of the method used, all programming of flash memory is done with the table read and table write instructions. these allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. the 24-bit target address in the program memory is formed using bits <7:0> of the tblpag register and the effective address (ea) fr om a w register specified in the table instruction, as shown in figure 4-1. the tblrdl and the tblwtl instructions are used to read or write to the bits<15:0> of program memory. tblrdl and tblwtl can access program memory in both word and byte modes. the tblrdh and tblwth instructions are used to read or write to bits<23:16> of program memory. tblrdh and tblwth can also access program memory in word or byte mode. figure 4-1: addressing for table registers note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . 0 program counter 24 bits program counter tblpag reg 8 bits working reg ea 16 bits byte 24-bit ea 0 1/0 select using table instruction using user/configuration space select
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 42 preliminary ? 2007 microchip technology inc. 4.2 rtsp operation the PIC24HJ32GP202/204 and pic24hj16gp304 flash program memory array is organized into rows of 64 instructions or 192 bytes. rtsp allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to pro- gram one row or one word at a time. the 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. the program memory implements holding buffers that can contain 64 instructions of programming data. prior to the actual programming operation, the write data must be loaded into the buffers sequentially. the instruction words loaded must always be from a group of 64 boundary. the basic sequence for rtsp programming is to set up a table pointer, then do a series of tblwt instructions to load the buffers. programming is performed by set- ting the control bits in the nvmcon register. a total of 64 tblwtl and tblwth instructions are required to load the instructions. all table write operations are single-word writes (two instruction cycles) because only the buffers are written. a programming cycle is required for programming each row. 4.3 control registers two sfrs are used to read and write the program flash memory: ? nvmcon: flash memory control register ? nvmkey: non-volatile memory key register the nvmcon register (register 4-1) controls which blocks need to be erased, which memory type is to be programmed and the start of the programming cycle. nvmkey (register 4-2) is a write-only register that is used for write protection. to start a programming or erase sequence, the user application must consecu- tively write 55h and aah to the nvmkey register. refer to section 4.4 ?programming operations? for further details. 4.4 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. a programming operation is nominally 4 ms in duration and the processor stalls (waits) until the oper- ation is finished. setting the wr bit (nvmcon<15>) starts the operation, and the wr bit is automatically cleared when the operation is finished.
? 2007 microchip technology inc. preliminary ds70289a-page 43 PIC24HJ32GP202/204 and pic24hj16gp304 register 4-1: nvmcon: flash memory control register r/so-0 (1) r/w-0 (1) r/w-0 (1) u-0 u-0 u-0 u-0 u-0 wr wren wrerr ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 (1) u-0 u-0 r/w-0 (1) r/w-0 (1) r/w-0 (1) r/w-0 (1) ? erase ? ?nvmop<3:0> (2) bit 7 bit 0 legend: so = satiable only bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 wr: write control bit 1 = initiates a flash memory program or erase operation. the operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = program or erase operation is complete and inactive bit 14 wren: write enable bit 1 = enable flash program/erase operations 0 = inhibit flash program/erase operations bit 13 wrerr: write sequence error flag bit 1 = an improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the wr bit) 0 = the program or erase operation completed normally bit 12-7 unimplemented: read as ? 0 ? bit 6 erase: erase/program enable bit 1 = perform the erase operation specified by nvmop<3:0> on the next wr command 0 = perform the program operation specified by nvmop<3:0> on the next wr command bit 5-4 unimplemented: read as ? 0 ? bit 3-0 nvmop<3:0>: nvm operation select bits (2) if erase = 1 : 1111 = memory bulk erase operation 1101 = erase general segment 1100 = erase secure segment 0011 = no operation 0010 = memory page erase operation 0001 = no operation 0000 = erase a single configuration register byte if erase = 0 : 1111 = no operation 1101 = no operation 1100 = no operation 0011 = memory word program operation 0010 = no operation 0001 = memory row program operation 0000 = program a single configuration register byte note 1: these bits can only be reset on por. 2: all other combinations of nvmop<3:0> are unimplemented.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 44 preliminary ? 2007 microchip technology inc. register 4-2: nvmkey: non-vo latile memory key register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<7:0> bit 7 bit 0 legend: so = satiable only bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 nvmkey<7:0>: key register (write only) bits
? 2007 microchip technology inc. preliminary ds70289a-page 45 PIC24HJ32GP202/204 and pic24hj16gp304 4.4.1 programming algorithm for flash program memory programmers can program one row of program flash memory at a time. to do this, it is necessary to erase the 8-row erase page that contains the desired row. the general process is: 1. read eight rows of program memory (512 instructions) and store in data ram. 2. update the program data in ram with the desired new data. 3. erase the block (see example 4-1): a) set the nvmop bits (nvmcon<3:0>) to ? 0010 ? to configure for block erase. set erase (nvmcon<6>) and wren (nvm- con<14>) bits. b) write the starting address of the page to be erased into the tblpag and w registers. c) write 55h to nvmkey. d) write aah to nvmkey. e) set the wr bit (nvmcon<15>). the erase cycle begins and the cpu stalls for the dura- tion of the erase cycle. when the erase is done, the wr bit is cleared automatically. 4. write the first 64 instructions from data ram into the program memory buffers (see example 4-2). 5. write the program block to flash memory: a) set the nvmop bits to ? 0001 ? to configure for row programming. clear the erase bit and set the wren bit. b) write 55h to nvmkey. c) write aah to nvmkey. d) set the wr bit. the programming cycle begins and the cpu stalls for the duration of the write cycle. when the write to flash mem- ory is done, the wr bit is cleared automatically. 6. repeat steps 4 and 5, using the next available 64 instructions from the block in data ram by incrementing the value in tblpag, until all 512 instructions are written back to flash mem- ory. to protect against accidental operations, the write ini- tiate sequence for nvmkey must be used to allow any erase or program operation to proceed. after the pro- gramming command has been executed, the user application must wait for the programming time until programming is complete. the two instructions following the start of the programming sequence should be nop s, as shown in example 4-3. example 4-1: erasing a program memory page ; set up nvmcon for block erase operation mov #0x4042, w0 ; mov w0, nvmcon ; initialize nvmcon ; init pointer to row to be erased mov #tblpage(prog_addr), w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #tbloffset(prog_addr), w0 ; initialize in-page ea[15:0] pointer tblwtl w0, [w0] ; set base address of erase block disi #5 ; block all interrupts with priority <7 ; for next 5 instructions mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequence nop ; insert two nops after the erase nop ; command is asserted
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 46 preliminary ? 2007 microchip technology inc. example 4-2: loading the write buffers example 4-3: initiating a programming sequence ; set up nvmcon for row programming operations mov #0x4001, w0 ; mov w0, nvmcon ; initialize nvmcon ; set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled mov #0x0000, w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #0x6000, w0 ; an example program memory address ; perform the tblwt instructions to write the latches ; 0th_program_word mov #low_word_0, w2 ; mov #high_byte_0, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 1st_program_word mov #low_word_1, w2 ; mov #high_byte_1, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 2nd_program_word mov #low_word_2, w2 ; mov #high_byte_2, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ? ? ? ; 63rd_program_word mov #low_word_31, w2 ; mov #high_byte_31, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch disi #5 ; block all interrupts with priority <7 ; for next 5 instructions mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequence nop ; insert two nops after the nop ; erase command is asserted
? 2007 microchip technology inc. preliminary ds70289a-page 47 PIC24HJ32GP202/204 and pic24hj16gp304 5.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst . the following is a list of device reset sources: ? por: power-on reset ? bor: brown-out reset ?mclr : master clear pin reset ?swr: reset instruction ? wdto: watchdog timer reset ? trapr: trap conflict reset ? iopuwr: illegal opcode, uninitialized w regis- ter reset, and security reset ? cm: configuration mismatch reset figure 5-1 shows the simplified block diagram of the reset module. any active source of reset makes the sysrst signal active. many registers associated with the cpu and peripherals are forced to a known reset state. most registers are unaffected by a reset; their status is unknown on por and unchanged by all other resets. all types of device reset will set a corresponding status bit in the rcon register to indicate the type of reset (see register 5-1). a por will clear all bits, except for the por bit (rcon<0>), that are set. the user appli- cation can set or clear any bit at any time during code execution. the rcon bits only serve as status bits. setting a particular reset status bit in software does not cause a device reset to occur. the rcon register also has other bits associated with the watchdog timer and device power-saving states. the function of these bits is discussed in other sections of this manual. figure 5-1: reset sy stem block diagram note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . note: refer to the specific peripheral or cpu section of this manual for register reset states. note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset will be meaningful. mclr v dd internal regulator bor sleep or idle reset instruction wdt module glitch filter trap conflict illegal opcode uninitialized w register sysrst v dd rise detect por configuration mismatch
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 48 preliminary ? 2007 microchip technology inc. register 5-1: rcon: re set control register (1) r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 trapr iopuwr ? ? ? ?cmvregs bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 extr swr swdten (2) wdto sleep idle bor por bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 trapr: trap reset flag bit 1 = a trap conflict reset has occurred 0 = a trap conflict reset has not occurred bit 14 iopuwr: illegal opcode or uninitialized w access reset flag bit 1 = an illegal opcode detection, an illegal address mode or uninitialized w register used as an address pointer caused a reset 0 = an illegal opcode or uninitialized w reset has not occurred bit 13-10 unimplemented: read as ? 0 ? bit 9 cm: configuration mismatch flag bit 1 = a configuration mismatch reset has occurred. 0 = a configuration mismatch reset has not occurred. bit 8 vregs: voltage regulator standby during sleep bit 1 = voltage regulator is active during sleep 0 = voltage regulator goes into standby mode during sleep bit 7 extr: external reset (mclr ) pin bit 1 = a master clear (pin) reset has occurred 0 = a master clear (pin) reset has not occurred bit 6 swr: software reset (instruction) flag bit 1 = a reset instruction has been executed 0 = a reset instruction has not been executed bit 5 swdten: software enable/disable of wdt bit (2) 1 = wdt is enabled 0 = wdt is disabled bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred bit 3 sleep: wake-up from sleep flag bit 1 = device has been in sleep mode 0 = device has not been in sleep mode bit 2 idle: wake-up from idle flag bit 1 = device was in idle mode 0 = device was not in idle mode note 1: all of the reset status bits can be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is ? 1 ? (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting.
? 2007 microchip technology inc. preliminary ds70289a-page 49 PIC24HJ32GP202/204 and pic24hj16gp304 table 5-1: reset flag bit operation bit 1 bor: brown-out reset flag bit 1 = a brown-out reset has occurred 0 = a brown-out reset has not occurred bit 0 por: power-on reset flag bit 1 = a power-up reset has occurred 0 = a power-up reset has not occurred flag bit setting event clearing event trapr (rcon<15>) trap conflict event por, bor iopuwr (rcon<14>) illegal opcode or uninitialized w register access por, bor cm (rcon<9>) configuration mismatch por, bor extr (rcon<7>) mclr reset por swr (rcon<6>) reset instruction por, bor wdto (rcon<4>) wdt time-out pwrsav instruction, por, bor, clrwdt instruction sleep (rcon<3>) pwrsav #sleep instruction por, bor idle (rcon<2>) pwrsav #idle instruction por, bor bor (rcon<1>) bor ? por (rcon<0>) por ? note: all reset flag bits may be set or cleared by the user software. register 5-1: rcon: re set control register (1) note 1: all of the reset status bits can be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is ? 1 ? (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 50 preliminary ? 2007 microchip technology inc. 5.1 clock source selection at reset if clock switching is enabled, the system clock source at device reset is chosen as shown in table 5-2. if clock switching is disabled, the system clock source is always selected according to the oscillator configuration bits. refer to section 7.0 ?oscillator configuration? for further details. table 5-2: oscillator selection vs. type of reset (clock switching enabled) 5.2 device reset times the reset times for various types of device reset are summarized in table 5-3. the system reset signal, sysrst , is released after the por and pwrt delay times expire. the time at which the device actually begins to execute code also depends on the system oscillator delays, which include the oscillator start-up timer (ost) and the pll lock time. the ost and pll lock times occur in parallel with the applicable sysrst delay times. the fscm delay determines the time at which the fscm begins to monitor the system clock source after the sysrst signal is released. table 5-3: reset delay times for various device resets reset type clock source determinant por oscillator configuration bits (fnosc<2:0>) bor mclr cosc control bits (osccon<14:12>) wdtr swr reset type clock source sysrst delay system clock delay fscm delay notes por ec, frc, lprc t por + t startup + t rst ?? 1, 2, 3 ecpll, frcpll t por + t startup + t rst t lock t fscm 1, 2, 3, 5, 6 xt, hs, sosc t por + t startup + t rst t ost t fscm 1, 2, 3, 4, 6 xtpll, hspll t por + t startup + t rst t ost + t lock t fscm 1, 2, 3, 4, 5, 6 bor ec, frc, lprc t startup + t rst ?? 3 ecpll, frcpll t startup + t rst t lock t fscm 3, 5, 6 xt, hs, sosc t startup + t rst t ost t fscm 3, 4, 6 xtpll, hspll t startup + t rst t ost + t lock t fscm 3, 4, 5, 6 mclr any clock t rst ?? 3 wdt any clock t rst ?? 3 software any clock t rst ?? 3 illegal opcode any clock t rst ?? 3 uninitialized w any clock t rst ?? 3 trap conflict any clock t rst ?? 3 note 1: t por = power-on reset delay (10 s nominal). 2: t startup = conditional por delay of 20 s nominal (if on-chip regulator is enabled) or 64 ms nominal power-up timer delay (if regulator is disabled). t startup is also applied to all returns from powered-down states, including waking from sleep mode, only if the regulator is enabled. 3: t rst = internal state reset time (20 s nominal). 4: t ost = oscillator start-up timer. a 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. 5: t lock = pll lock time (20 s nominal). 6: t fscm = fail-safe clock monitor delay (100 s nominal).
? 2007 microchip technology inc. preliminary ds70289a-page 51 PIC24HJ32GP202/204 and pic24hj16gp304 5.2.1 por and long oscillator start-up times the oscillator start-up circuitry and its associated delay timers are not linked to the device reset delays that occur at power-up. some crystal circuits (especially low-frequency crystals) have a relatively long start-up time. therefore, one or more of the following conditions is possible after sysrst is released. ? the oscillator circuit has not begun to oscillate. ? the oscillator start-up timer has not expired (if a crystal oscillator is used). ? the pll has not achieved a lock (if pll is used). the device will not begin to execute code until a valid clock source has been released to the system. there- fore, the oscillator and the pll start-up delays must be considered when the reset delay time must be known. 5.2.2 fail-safe clock monitor (fscm) and device resets if the fscm is enabled, it begins to monitor the system clock source when sysrst is released. if a valid clock source is not available, the device automatically switches to the frc oscillator and the user application can switch to the desired crystal oscillator in the trap service routine. 5.2.2.1 fscm delay for crystal and pll clock sources when the system clock source is provided by a crystal oscillator and/or the pll, a short delay, t fscm , is auto- matically inserted after the por and pwrt delay times. the fscm does not start to monitor the system clock source until this delay expires. the fscm delay time is nominally 500 s and provides additional time for the oscillator and/or pll to stabilize. in most cases, the fscm delay prevents an oscillator failure trap at a device reset when the pwrt is disabled. 5.3 special function register reset states most of the special function registers (sfrs) associ- ated with the cpu and peripherals are reset to a particular value at a device reset. the sfrs are grouped by their peripheral or cpu function, and their reset values are specified in each section of this man- ual. the reset value for each sfr does not depend on the type of reset, with the exception of two registers: ? the reset value for the reset control register, rcon, depends on the type of device reset. ? the reset value for the oscillator control regis- ter, osccon, depends on the type of reset and the programmed values of the oscillator configu- ration bits in the fosc configuration register.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 52 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70289a-page 53 PIC24HJ32GP202/204 and pic24hj16gp304 6.0 interrupt controller the PIC24HJ32GP202/204 and pic24hj16gp304 interrupt controllers reduce the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24HJ32GP202/204 and pic24hj16gp304 cpu. it has the following features: ? up to 8 processor exceptions and software traps ? 7 user-selectable priority levels ? interrupt vector table (ivt) with up to 118 vectors ? a unique vector for each interrupt or exception source ? fixed priority within a specified user priority level ? alternate interrupt vector table (aivt) for debug support ? fixed interrupt entry and return latencies 6.1 interrupt vector table figure 6-1 shows the interrrupt vector table. the ivt resides in program memory, starting at location 000004h. the ivt contains 126 vectors consisting of 8 nonmaskable trap vectors and up to 118 sources of interrupt. in general, each interrupt source has its own vector. each interrupt vector contains a 24-bit wide address. the value programmed into each interrupt vector location is the starting address of the associated interrupt service routine (isr). interrupt vectors are prioritized in terms of their natural priority; this priority is linked to their position in the vector table. lower addresses generally have a higher natural priority. for example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. PIC24HJ32GP202/204 and pic24hj16gp304 devices implement up to 21 unique interrupts and 4 non- maskable traps. these are summarized in table 6-1 and table 6-2. 6.1.1 alternate interrupt vector ta b l e the alternate interrupt vector table (aivt) is located after the ivt, as shown in figure 6-1. access to the aivt is provided by the altivt control bit (intcon2<15>). if the altivt bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. the alternate vectors are organized in the same manner as the default vectors. the aivt supports debugging by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. this feature also enables switching between applications for evaluation of different software algorithms at run time. if the aivt is not needed, the aivt should be programmed with the same addresses used in the ivt. 6.2 reset sequence a device reset is not a true exception because the interrupt controller is not involved in the reset process. the PIC24HJ32GP202/204 and pic24hj16gp304 device clear its registers in response to a reset, which forces the pc to zero. the microcontroller then begins the program execution at location 0x000000. the user application can use a goto instruction at the reset address which redirects program execution to the appropriate start-up routine. note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . note: any unimplemented or unused vector locations in the ivt and aivt should be programmed with the address of a default interrupt handler routine that contains a reset instruction.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 54 preliminary ? 2007 microchip technology inc. figure 6-1: PIC24HJ32GP202/204 and pi c24hj16gp304 interrupt vector table reset ? goto instruction 0x000000 reset ? goto address 0x000002 reserved 0x000004 oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 0x000014 interrupt vector 1 ~ ~ ~ interrupt vector 52 0x00007c interrupt vector 53 0x00007e interrupt vector 54 0x000080 ~ ~ ~ interrupt vector 116 0x0000fc interrupt vector 117 0x0000fe reserved 0x000100 reserved 0x000102 reserved oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 0x000114 interrupt vector 1 ~ ~ ~ interrupt vector 52 0x00017c interrupt vector 53 0x00017e interrupt vector 54 0x000180 ~ ~ ~ interrupt vector 116 interrupt vector 117 0x0001fe start of code 0x000200 decreasing natural order priority interrupt vector table (ivt) (1) alternate interrupt vector table (aivt) (1) note 1: see table 6-1 for the list of implemented interrupt vectors.
? 2007 microchip technology inc. preliminary ds70289a-page 55 PIC24HJ32GP202/204 and pic24hj16gp304 table 6-1: interrupt vectors vector number interrupt request (irq) number ivt address aivt addr ess interrupt source 8 0 0x000014 0x000114 int0 ? external interrupt 0 9 1 0x000016 0x000116 ic1 ? input compare 1 10 2 0x000018 0x000118 oc1 ? output compare 1 11 3 0x00001a 0x00011a t1 ? timer1 12 4 0x00001c 0x00011c reserved 13 5 0x00001e 0x00011e ic2 ? input capture 2 14 6 0x000020 0x000120 oc2 ? output compare 2 15 7 0x000022 0x000122 t2 ? timer2 16 8 0x000024 0x000124 t3 ? timer3 17 9 0x000026 0x000126 spi1e ? spi1 error 18 10 0x000028 0x000128 spi1 ? spi1 transfer done 19 11 0x00002a 0x00012a u1rx ? uart1 receiver 20 12 0x00002c 0x00012c u1tx ? uart1 transmitter 21 13 0x00002e 0x00012e adc1 ? adc 1 22 14 0x000030 0x000130 reserved 23 15 0x000032 0x000132 reserved 24 16 0x000034 0x000134 si2c1 ? i2c1 slave events 25 17 0x000036 0x000136 mi2c1 ? i2c1 master events 26 18 0x000038 0x000138 reserved 27 19 0x00003a 0x00013a change notification interrupt 28 20 0x00003c 0x00013c int1 ? external interrupt 1 29 21 0x00003e 0x00013e reserved 30 22 0x000040 0x000140 ic7 ? input capture 7 31 23 0x000042 0x000142 ic8 ? input capture 8 32 24 0x000044 0x000144 reserved 33 25 0x000046 0x000146 reserved 34 26 0x000048 0x000148 reserved 35 27 0x00004a 0x00014a reserved 36 28 0x00004c 0x00014c reserved 37 29 0x00004e 0x00014e int2 ? external interrupt 2 38 30 0x000050 0x000150 reserved 39 31 0x000052 0x000152 reserved 40 32 0x000054 0x000154 reserved 41 33 0x000056 0x000156 reserved 42 34 0x000058 0x000158 reserved 43 35 0x00005a 0x00015a reserved 44 36 0x00005c 0x00015c reserved 45 37 0x00005e 0x00015e reserved 46 38 0x000060 0x000160 reserved 47 39 0x000062 0x000162 reserved 48 40 0x000064 0x000164 reserved 49 41 0x000066 0x000166 reserved 50 42 0x000068 0x000168 reserved 51 43 0x00006a 0x00016a reserved 52 44 0x00006c 0x00016c reserved 53 45 0x00006e 0x00016e reserved
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 56 preliminary ? 2007 microchip technology inc. table 6-2: trap vectors 54 46 0x000070 0x000170 reserved 55 47 0x000072 0x000172 reserved 56 48 0x000074 0x000174 reserved 57 49 0x000076 0x000176 reserved 58 50 0x000078 0x000178 reserved 59 51 0x00007a 0x00017a reserved 60 52 0x00007c 0x00017c reserved 61 53 0x00007e 0x00017e reserved 62 54 0x000080 0x000180 reserved 63 55 0x000082 0x000182 reserved 64 56 0x000084 0x000184 reserved 65 57 0x000086 0x000186 reserved 66 58 0x000088 0x000188 reserved 67 59 0x00008a 0x00018a reserved 68 60 0x00008c 0x00018c reserved 69 61 0x00008e 0x00018e reserved 70 62 0x000090 0x000190 reserved 71 63 0x000092 0x000192 reserved 72 64 0x000094 0x000194 reserved 73 65 0x000096 0x000196 u1e ? uart1 error 74 66 0x000098 0x000198 reserved 75 67 0x00009a 0x00019a reserved 76 68 0x00009c 0x00019c reserved 77 69 0x00009e 0x00019e reserved 78 70 0x0000a0 0x0001a0 reserved 79 71 0x0000a2 0x0001a2 reserved 80-125 72-117 0x0000a4- 0x0000fe 0x0001a4- 0x0001fe reserved vector number ivt addres s aivt address trap source 0 0x000004 0x000104 reserved 1 0x000006 0x000106 oscillator failure 2 0x000008 0x000108 address error 3 0x00000a 0x00010a stack error 4 0x00000c 0x00010c math error 5 0x00000e 0x00010e reserved 6 0x000010 0x000110 reserved 7 0x000012 0x000112 reserved table 6-1: interrupt vectors (continued) vector number interrupt request (irq) number ivt address aivt addr ess interrupt source
? 2007 microchip technology inc. preliminary ds70289a-page 57 PIC24HJ32GP202/204 and pic24hj16gp304 6.3 interrupt control and status registers PIC24HJ32GP202/204 and pic24hj16gp304 devices implement a total of 17 registers for the inter- rupt controller: ? interrupt control register 1 (intcon1) ? interrupt control register 2 (intcon2) ? interrupt flag status registers (ifsx) ? interrupt enable control registers (iecx) ? interrupt priority control registers (ipcx) ? interrupt control and status register (inttreg) 6.3.1 intcon1 and intcon2 global interrupt control functions are controlled from intcon1 and intcon2. intcon1 contains the interrupt nesting disable (nstdis) bit as well as the control and status flags for the processor trap sources. the intcon2 register controls the external interrupt request signal behavior and the use of the alternate interrupt vector table. 6.3.2 ifsx the ifs registers maintain all the interrupt request flags. each source of interrupt has a status bit, which is set by the respective peripherals or external signal and this is cleared via software. 6.3.3 iecx the iec registers maintain all the interrupt enable bits. these control bits are used individually to enable inter- rupts from the peripherals or external signals. 6.3.4 ipcx the ipc registers are used to set the interrupt priority level for each source of interrupt. each user interrupt source can be assigned to one of the eight priority lev- els. 6.3.5 inttreg the inttreg register contains the associated interrupt vector number and the new cpu interrupt priority level, which are latched into vector number (vecnum<6:0>) and interrupt level (ilr<3:0>) bit fields in the inttreg register. the new interrupt priority level is the priority of the pending interrupt. the interrupt sources are assigned to the ifsx, iecx and ipcx registers in the same sequence that they are listed in table 6-1. for example, the int0 (external interrupt 0) is shown as having vector number 8 and a natural order priority of 0. thus, the int0if bit is found in ifs0<0>, the int0ie bit in iec0<0>, and the int0ip bits in the first position of ipc0 (ipc0<2:0>). 6.3.6 status registers although these are not specifically part of the interrupt control hardware, two of the cpu control registers contain bits that control interrupt functionality: ? the cpu status register, sr, contains the ipl<2:0> bits (sr<7:5>). these bits indicate the current cpu interrupt priority level. the user can change the current cpu priority level by writing to the ipl bits. ? the corcon register contains the ipl3 bit which, together with ipl<2:0>, also indicates the current cpu priority level. ipl3 is a read-only bit, so that trap events cannot be masked by the user software. all interrupt registers are described in register 6-1 through register 6-19 in the following pages.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 58 preliminary ? 2007 microchip technology inc. register 6-1: sr: cpu status register (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?dc bit 15 bit 8 r/w-0 (3) r/w-0 (3) r/w-0 (3) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl2 (2) ipl1 (2) ipl0 (2) ra n ov z c bit 7 bit 0 legend: c = clear only bit r = readable bit u = unimplemented bit, read as ?0? s = set only bit w = writable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 ipl<2:0>: cpu interrupt priority level status bits (1) 111 = cpu interrupt priority level is 7 (15), user interrupts disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) note 1: for complete register details, see register 2-1: ?sr: cpu status register? . 2: the ipl<2:0> bits are concatenated with the ipl<3> bit (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read-only when nstdis (intcon1<15>) = 1 .
? 2007 microchip technology inc. preliminary ds70289a-page 59 PIC24HJ32GP202/204 and pic24hj16gp304 register 6-2: corcon: core control register (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r/c-0 r/w-0 u-0 u-0 ? ? ? ? ipl3 (2) psv ? ? bit 7 bit 0 legend: c = clear only bit r = readable bit w = writable bit -n = value at por ?1? = bit is set 0? = bit is cleared ?x = bit is unknown u = unimplemented bit, read as ?0? bit 3 ipl3: cpu interrupt priority level status bit 3 (2) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less note 1: for complete register details, see register 2-2: ?corcon: core control register? . 2: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 60 preliminary ? 2007 microchip technology inc. register 6-3: intcon1: in terrupt control register 1 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 nstdis ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 ?div0err ? matherr addrerr stkerr oscfail ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 nstdis: interrupt nesting disable bit 1 = interrupt nesting is disabled 0 = interrupt nesting is enabled bit 14-7 unimplemented: read as ? 0 ?. bit 6 div0err: arithmetic error status bit 1 = math error trap was caused by a divide by zero 0 = math error trap was not caused by a divide by zero bit 5 unimplemented: read as ? 0 ? bit 4 matherr: arithmetic error status bit 1 = math error trap has occurred 0 = math error trap has not occurred bit 3 addrerr: address error trap status bit 1 = address error trap has occurred 0 = address error trap has not occurred bit 2 stkerr: stack error trap status bit 1 = stack error trap has occurred 0 = stack error trap has not occurred bit 1 oscfail: oscillator failure trap status bit 1 = oscillator failure trap has occurred 0 = oscillator failure trap has not occurred bit 0 unimplemented: read as ? 0 ?
? 2007 microchip technology inc. preliminary ds70289a-page 61 PIC24HJ32GP202/204 and pic24hj16gp304 register 6-4: intcon2: in terrupt control register 2 r/w-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 altivt disi ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? int2ep int1ep int0ep bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 altivt: enable alternate interrupt vector table bit 1 = use alternate vector table 0 = use standard (default) vector table bit 14 disi: disi instruction status bit 1 = disi instruction is active 0 = disi instruction is not active bit 13-3 unimplemented: read as ? 0 ? bit 2 int2ep: external interrupt 2 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 1 int1ep: external interrupt 1 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 0 int0ep: external interrupt 0 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 62 preliminary ? 2007 microchip technology inc. register 6-5: ifs0: interrupt flag status register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ad1if u1txif u1rxif spi1if spi1eif t3if bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 t2if oc2if ic2if ? t1if oc1if ic1if int0if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-4 unimplemented: read as ? 0 ? bit 13 ad1if: adc1 conversion complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 u1txif: uart1 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 u1rxif: uart1 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 spi1if: spi1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 spi1eif: spi1 fault interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 t3if: timer3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7 t2if: timer2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 oc2if: output compare channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 ic2if: input capture channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4 unimplemented: read as ? 0 ? bit 3 t1if: timer1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 oc1if: output compare channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
? 2007 microchip technology inc. preliminary ds70289a-page 63 PIC24HJ32GP202/204 and pic24hj16gp304 bit 1 ic1if: input capture channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 int0if: external interrupt 0 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred register 6-5: ifs0: interrupt fla g status register 0 (continued)
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 64 preliminary ? 2007 microchip technology inc. register 6-6: ifs1: interrupt flag status register 1 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?int2if ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 ic8if ic7if ? int1if cnif ? mi2c1if si2c1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-4 unimplemented: read as ? 0 ? bit 13 int2if: external interrupt 2 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12-8 unimplemented: read as ? 0 ? bit 7 ic8if: input capture channel 8 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 ic7if: input capture channel 7 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 unimplemented: read as ? 0 ? bit 4 int1if: external interrupt 1 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 cnif: input change notification interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 unimplemented: read as ? 0 ? bit 1 mi2c1if: i2c1 master events interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 si2c1if: i2c1 slave events interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
? 2007 microchip technology inc. preliminary ds70289a-page 65 PIC24HJ32GP202/204 and pic24hj16gp304 register 6-7: ifs4: interrupt flag status register 4 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ?u1eif ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as ? 0 ? bit 1 u1eif: uart1 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 unimplemented: read as ? 0 ?
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 66 preliminary ? 2007 microchip technology inc. register 6-8: iec0: interrupt enable control register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ad1ie u1txie u1rxie spi1ie spi1eie t3ie bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 t2ie oc2ie ic2ie ? t1ie oc1ie ic1ie int0ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-4 unimplemented: read as ? 0 ? bit 13 ad1ie: adc1 conversion complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12 u1txie: uart1 transmitter interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 11 u1rxie: uart1 receiver interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 10 spi1ie: spi1 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 9 spi1eie: spi1 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 8 t3ie: timer3 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 7 t2ie: timer2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 6 oc2ie: output compare channel 2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 5 ic2ie: input capture channel 2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 4 unimplemented: read as ? 0 ? bit 3 t1ie: timer1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 oc1ie: output compare channel 1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled
? 2007 microchip technology inc. preliminary ds70289a-page 67 PIC24HJ32GP202/204 and pic24hj16gp304 bit 1 ic1ie: input capture channel 1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 int0ie: external interrupt 0 enable bit 1 = interrupt request enabled 0 = interrupt request not enabled register 6-8: iec0: interrupt enable control register 0 (continued)
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 68 preliminary ? 2007 microchip technology inc. register 6-9: iec1: interrupt enable control register 0 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?int2ie ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 ic8ie ic7ie ? int1ie cnie ? mi2c1ie si2c1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 int2ie: external interrupt 2 enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12-8 unimplemented: read as ? 0 ? bit 7 ic8ie: input capture channel 8 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 6 ic7ie: input capture channel 7 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 5 unimplemented: read as ? 0 ? bit 4 int1ie: external interrupt 1 enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 3 cnie: input change notification interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 unimplemented: read as ? 0 ? bit 1 mi2c1ie: i2c1 master events interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 si2c1ie: i2c1 slave events interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled
? 2007 microchip technology inc. preliminary ds70289a-page 69 PIC24HJ32GP202/204 and pic24hj16gp304 register 6-10: iec4: interrupt enable control register 0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 ? ? ? ? ? ?u1eie ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as ? 0 ? bit 1 u1eie: uart1 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 unimplemented: read as ? 0 ?
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 70 preliminary ? 2007 microchip technology inc. register 6-11: ipc0: interrupt priority control register 0 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? t1ip<2:0> ? oc1ip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ic1ip<2:0> ? int0ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t1ip<2:0>: timer1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc1ip<2:0>: output compare channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic1ip<2:0>: input capture channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 int0ip<2:0>: external interrupt 0 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2007 microchip technology inc. preliminary ds70289a-page 71 PIC24HJ32GP202/204 and pic24hj16gp304 register 6-12: ipc1: interrupt pr iority control register 1 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? t2ip<2:0> ? oc2ip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ic2ip<2:0> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t2ip<2:0>: timer2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc2ip<2:0>: output compare channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic2ip<2:0>: input capture channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 72 preliminary ? 2007 microchip technology inc. register 6-13: ipc2: interrupt pr iority control register 2 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? u1rxip<2:0> ? spi1ip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? spi1eip<2:0> ? t3ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 u1rxip<2:0>: uart1 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 spi1ip<2:0>: spi1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 spi1eip<2:0>: spi1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 t3ip<2:0>: timer3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2007 microchip technology inc. preliminary ds70289a-page 73 PIC24HJ32GP202/204 and pic24hj16gp304 register 6-14: ipc3: interrupt pr iority control register 3 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ad1ip<2:0> ? u1txip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 ad1ip<2:0>: adc1 conversion complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 u1txip<2:0>: uart1 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 74 preliminary ? 2007 microchip technology inc. register 6-15: ipc4: interrupt pr iority control register 4 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ?cnip<2:0> ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? mi2c1ip<2:0> ? si2c1ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 cnip<2:0>: change notification interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11-7 unimplemented: read as ? 0 ? bit 6-4 mi2c1ip<2:0>: i2c1 master events interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 si2c1ip<2:0>: i2c1 slave events interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2007 microchip technology inc. preliminary ds70289a-page 75 PIC24HJ32GP202/204 and pic24hj16gp304 register 6-16: ipc5: interrupt pr iority control register 5 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ic8ip<2:0> ?ic7ip<2:0> bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? int1ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 ic8ip<2:0>: input capture channel 8 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 ic7ip<2:0>: input capture channel 7 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7-3 unimplemented: read as ? 0 ? bit 2-0 int1ip<2:0>: external interrupt 1 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 76 preliminary ? 2007 microchip technology inc. register 6-17: ipc7: interrupt pr iority control register 7 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? int2ip<2:0> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 int2ip<2:0>: external interrupt 2 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
? 2007 microchip technology inc. preliminary ds70289a-page 77 PIC24HJ32GP202/204 and pic24hj16gp304 register 6-18: ipc16: interrupt priority control register 16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? u1eip<2:0> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 u1eip<2:0>: uart1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 78 preliminary ? 2007 microchip technology inc. register 6-19: inttreg: interrupt control and status register u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ? ? ? ?ilr<3:0> bit 15 bit 8 u-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? vecnum<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 11-8 ilr: new cpu interrupt priority level bits 1111 = cpu interrupt priority level is 15 ? ? ? 0001 = cpu interrupt priority level is 1 0000 = cpu interrupt priority level is 0 bit 7 unimplemented: read as ? 0 ? bit 6-0 vecnum: vector number of pending interrupt bits 0111111 = interrupt vector pending is number 135 ? ? ? 0000001 = interrupt vector pending is number 9 0000000 = interrupt vector pending is number 8
? 2007 microchip technology inc. preliminary ds70289a-page 79 PIC24HJ32GP202/204 and pic24hj16gp304 6.4 interrupt setup procedures 6.4.1 initialization to configure an interrupt source at initialization: 1. set the nstdis bit (intcon1<15>) if nested interrupts are not desired. 2. select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate ipcx register. the priority level will depend on the specific application and type of interrupt source. if multiple priority levels are not desired, the ipcx register control bits for all enabled interrupt sources can be programmed to the same non-zero value. 3. clear the interrupt flag status bit associated with the peripheral in the associated ifsx register. 4. set the interrupt enable control bit associated with the source in the appropriate iecx register to enable the interrupt source. 6.4.2 interrupt service routine the method used to declare an isr and initialize the ivt with the correct vector address depends on the programming language (c or assembler) and the lan- guage development toolsuite used to develop the appli- cation. in general, the user application must clear the interrupt flag in the appropriate ifsx register for the source of interrupt that the isr handles. otherwise, the program will re-enter the isr immediately after exiting the routine. if the isr is coded in assembly language, it must be terminated using a retfie instruction to unstack the saved pc value, srl value and old cpu priority level. 6.4.3 trap service routine a trap service routine (tsr) is coded like an isr, except that the appropriate trap status flag in the intcon1 register must be cleared to avoid re-entry into the tsr. 6.4.4 interrupt disable all user interrupts can be disabled using this proce- dure: 1. push the current sr value onto the software stack using the push instruction. 2. force the cpu to priority level 7 by inclusive oring the value oeh with srl. to enable user interrupts, the pop instruction can be used to restore the previous sr value. the disi instruction provides a convenient way to dis- able interrupts of priority levels 1-6 for a fixed period of time. level 7 interrupt sources are not disabled by the disi instruction. note: at a device reset, the ipcx registers are initialized such that all user interrupt sources are assigned to priority level 4. note: only user interrupts with a priority level of 7 or lower can be disabled. trap sources (level 8-level 15) cannot be disabled.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 80 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds-70289a-page 81 PIC24HJ32GP202/204 and pic24hj16gp304 7.0 oscillator configuration the PIC24HJ32GP202/204 and pic24hj16gp304 oscillator system provides: ? external and internal oscillator options as clock sources ? an on-chip pll to scale the internal operating frequency to the required system clock frequency ? an internal frc oscillator that can also be used with the pll, thereby allowing full speed operation without any external clock generation hardware ? clock switching between various clock sources ? programmable clock postscaler for system power savings ? a fail-safe clock monitor (fscm) that detects clock failure and takes fail-safe measures ? a clock control register (osccon) ? nonvolatile configuration bits for main oscillator selection. a simplified diagram of the oscillator system is shown in figure 7-1. figure 7-1: PIC24HJ32GP202/204 and pic2 4hj16gp304 oscillator system diagram note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . pic24h secondary oscillator lposcen sosco sosci timer 1 osci osco primary oscillator xtpll, hspll, xt, hs, ec frcdiv<2:0> wdt, pwrt, fscm frcdivn sosc frcdiv16 ecpll, frcpll nosc<2:0> fnosc<2:0> reset frc oscillator lprc oscillator doze<2:0> s3 s1 s2 s1/s3 s7 s6 frc lprc s0 s5 s4 16 clock switch s7 clock fail 2 tun<5:0> pll (1) f cy f osc frcdiv doze note 1: see figure 7-2 for pll details
PIC24HJ32GP202/204 and pic24hj16gp304 ds-70289a-page 82 preliminary ? 2007 microchip technology inc. 7.1 cpu clocking system the PIC24HJ32GP202/204 and pic24hj16gp304 devices provide the following seven system clock options. ? fast rc (frc) oscillator ? frc oscillator with pll ? primary (xt, hs or ec) oscillator ? primary oscillator with pll ? secondary (lp) oscillator ? low-power rc (lprc) oscillator ? frc oscillator with postscaler 7.1.1 system clock sources 7.1.1.1 fast rc the fast rc (frc) internal oscillator runs at a nominal frequency of 7.37 mhz. user software can tune the frc frequency. user software can optionally specify a factor (ranging from 1:2 to 1:256) by which the frc clock frequency is divided. this factor is selected using the frcdiv<2:0> (clkdiv<10:8>) bits. 7.1.1.2 primary the primary oscillator can use one of the following as its clock source: ? crystal (xt): crystals and ceramic resonators in the range of 3 mhz to 10 mhz. the crystal is con- nected to the osc1 and osc2 pins. ? hs (high-speed crystal): crystals in the range of 10 mhz to 40 mhz. the crystal is connected to the osc1 and osc2 pins. ? ec (external clock): external clock signal in the range of 0.8 mhz to 64 mhz. the external clock signal is directly applied to the osc1 pin. 7.1.1.3 secondary the secondary (lp) oscillator is designed for low power and uses a 32.768 khz crystal or ceramic resonator. the lp oscillator uses sosci and sosco pins. 7.1.1.4 low-power rc the low-power rc (lprc) internal oscillator runs at a nominal frequency of 32.768 khz. it is also used as a reference clock by the watchdog timer (wdt) and fail-safe clock monitor (fscm). 7.1.1.5 frc the clock signals generated by the frc and primary oscillators can be optionally applied to an on-chip phase locked loop (pll) to provide a wide range of output frequencies for device operation. pll configuration is described in section 7.1.3 ?pll configuration? . 7.1.2 system clock selection the oscillator source used at a device power-on reset event is selected using configuration bit settings. the oscillator configuration bit settings are located in the configuration registers in the program memory. (refer to section 18.1 ?configuration bits? for further details.) the initial oscillator selection configuration bits, fnosc<2:0> (foscsel<2:0>), and the primary oscil- lator mode select configuration bits, poscmd<1:0> (fosc<1:0>), select the oscillator source that is used at a power-on reset. the frc primary oscillator is the default (unprogrammed) selection. the configuration bits allow users to choose among 12 different clock modes, shown in table 7-1. the output of the oscillator (or the output of the pll if a pll mode has been selected) f osc is divided by 2 to generate the device instruction clock (f cy ). f cy defines the operating speed of the device, and speeds up to 40 mhz are supported by the PIC24HJ32GP202/ 204 and pic24hj16gp304 architecture. instruction execution speed or device operating frequency, f cy , is given by: equation 7-1: device operating frequency 7.1.3 pll configuration the primary oscillator and internal frc oscillator can optionally use on-chip pll to obtain higher speeds of operation. the pll provides significant flexibility in selecting the device operating speed. a block diagram of the pll is shown in figure 7-2. the output of the primary oscillator or frc, denoted as ?f in ? is divided down by a prescale factor (n1) of 2, 3, ... or 33 before it is being provided to the pll?s voltage controlled oscillator (vco). the input to the vco must be selected in the range of 0.8 mhz to 8 mhz. the prescale factor ?n1? is selected using the pllpre<4:0> bits (clkdiv<4:0>). the pll feedback divisor, selected using the plldiv<8:0> bits (pllfbd<8:0>), provides a factor ?m,? by which the input to the vco is multiplied. this factor must be selected such that the resulting vco output frequency is in the range of 100 mhz to 200 mhz. the vco output is further divided by a postscale factor ?n2.? this factor is selected using the pllpost<1:0> bits (clkdiv<7:6>). ?n2? can be 2, 4 or 8, and must be selected such that the pll output frequency (f osc ) is in the range of 12.5 mhz to 80 mhz, which generates device operating speeds of 6.25-40 mips. f cy = f osc /2
? 2007 microchip technology inc. preliminary ds-70289a-page 83 PIC24HJ32GP202/204 and pic24hj16gp304 for a primary oscillator or frc oscillator, output ?f in ?, the pll output ?f osc ? is given by: equation 7-2: f osc calculation for example, when a 10 mhz crystal is being used, with ?xt with pll? being the selected oscillator mode. ? if pllpre<4:0> = 0 , then n1 = 2. this yields a vco input of 10/2 = 5 mhz, which is within the acceptable range of 0.8-8 mhz. ? if plldiv<8:0> = 0x1e, then m = 32. this yields a vco output of 5 x 32 = 160 mhz, which is within the 100 mhz to 200 mhz range, which is needed. ? if pllpost<1:0> = 0 , then n2 = 2. this provides a fosc of 160/2 = 80 mhz. the resultant device operating speed is 80/2 = 40 mips. equation 7-3: xt with pll mode example figure 7-2: PIC24HJ32GP202/204 and pic24hj16gp304 pll block diagram table 7-1: configuration bit va lues for clock selection ( ) m n1*n2 f osc = f in * f cy = f osc = 1 ( 10000000*32 ) = 40 mips 2 2 2*2 oscillator mode oscillator source poscmd<1:0> fnosc<2:0> note fast rc oscillator with divide-by-n (frcdivn) internal xx 111 1, 2 fast rc oscillator with divide-by-16 (frcdiv16) internal xx 110 1 low-power rc oscillator (lprc) internal xx 101 1 secondary (timer1) oscillator (sosc) secondary xx 100 1 primary oscillator (hs) with pll (hspll) primary 10 011 primary oscillator (xt) with pll (xtpll) primary 01 011 primary oscillator (ec) with pll (ecpll) primary 00 011 1 primary oscillator (hs) primary 10 010 primary oscillator (xt) primary 01 010 primary oscillator (ec) primary 00 010 1 fast rc oscillator with pll (frcpll) internal xx 001 1 fast rc oscillator (frc) internal xx 000 1 note 1: osc2 pin function is determined by the osciofnc configuration bit. 2: this is the default oscillator mode for an unprogrammed (erased) device. 0.8-8.0 mhz here 100-200 mhz here divide by 2, 4, 8 divide by 2-513 divide by 2-33 source (crystal, external clock pllpre x vco plldiv pllpost or internal rc) 12.5-80 mhz here f osc
PIC24HJ32GP202/204 and pic24hj16gp304 ds-70289a-page 84 preliminary ? 2007 microchip technology inc. register 7-1: osccon: os cillator control register u-0 r-0 r-0 r-0 u-0 r/w-y r/w-y r/w-y ?cosc<2:0> ?nosc<2:0> bit 15 bit 8 r/w-0 r/w-0 r-0 u-0 r/c-0 u-0 r/w-0 r/w-0 clklock iolock lock ?cf ? lposcen oswen bit 7 bit 0 legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 cosc<2:0>: current oscillator selection bits (read-only) 000 = fast rc oscillator (frc) 001 = fast rc oscillator (frc) with pll 010 = primary oscillator (xt, hs, ec) 011 = primary oscillator (xt, hs, ec) with pll 100 = secondary oscillator (sosc) 101 = low-power rc oscillator (lprc) 110 = fast rc oscillator (frc) with divide-by-16 111 = fast rc oscillator (frc) with divide-by-n bit 11 unimplemented: read as ? 0 ? bit 10-8 nosc<2:0>: new oscillator selection bits 000 = fast rc oscillator (frc) 001 = fast rc oscillator (frc) with pll 010 = primary oscillator (xt, hs, ec) 011 = primary oscillator (xt, hs, ec) with pll 100 = secondary oscillator (sosc) 101 = low-power rc oscillator (lprc) 110 = fast rc oscillator (frc) with divide-by-16 111 = fast rc oscillator (frc) with divide-by-n bit 7 clklock: clock lock enable bit if clock switching is enabled and fscm is disabled (fosc = 0b01) 1 = clock switching is disabled, system clock source is locked 0 = clock switching is enabled, system clock source can be modified by clock switching bit 6 iolock: peripheral pin select lock bit 1 = peripherial pin select is locked, write to peripheral pin select register is not allowed 0 = peripherial pin select is unlocked, write to peripheral pin select register is allowed bit 5 lock: pll lock status bit (read-only) 1 = indicates that pll is in lock, or pll start-up timer is satisfied 0 = indicates that pll is out of lock, start-up timer is in progress or pll is disabled bit 4 unimplemented: read as ? 0 ? bit 3 cf: clock fail detect bit (read/clear by application) 1 = fscm has detected clock failure 0 = fscm has not detected clock failure bit 2 unimplemented: read as ? 0 ?
? 2007 microchip technology inc. preliminary ds-70289a-page 85 PIC24HJ32GP202/204 and pic24hj16gp304 bit 1 lposcen: secondary (lp) oscillator enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 0 oswen: oscillator switch enable bit 1 = request oscillator switch to selection specified by nosc<2:0> bits 0 = oscillator switch is complete register 7-1: osccon: oscillato r control register (continued)
PIC24HJ32GP202/204 and pic24hj16gp304 ds-70289a-page 86 preliminary ? 2007 microchip technology inc. register 7-2: clkdiv: clock divisor register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 roi doze<2:0> dozen (1) frcdiv<2:0> bit 15 bit 8 r/w-0 r/w-1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pllpost<1:0> ? pllpre<4:0> bit 7 bit 0 legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 roi: recover on interrupt bit 1 = interrupts will clear the dozen bit and the processor clock/peripheral clock ratio is set to 1:1 0 = interrupts have no effect on the dozen bit bit 14-12 doze<2:0>: processor clock reduction select bits 000 = f cy /1 001 = f cy /2 010 = f cy /4 011 = f cy /8 (default) 100 = f cy /16 101 = f cy /32 110 = f cy /64 111 = f cy /128 bit 11 dozen: doze mode enable bit (1) 1 = doze<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = processor clock/peripheral clock ratio forced to 1:1 bit 10-8 frcdiv<2:0>: internal fast rc oscillator postscaler bits 000 = frc divide by 1 (default) 001 = frc divide by 2 010 = frc divide by 4 011 = frc divide by 8 100 = frc divide by 16 101 = frc divide by 32 110 = frc divide by 64 111 = frc divide by 256 bit 7-6 pllpost<1:0>: pll vco output divider select bits (also denoted as ?n2?, pll postscaler) 00 = output/2 01 = output/4 (default) 10 = reserved 11 = output/8 bit 5 unimplemented: read as ? 0 ? bit 4-0 pllpre<4:0>: pll phase detector input divider bits (also denoted as ?n1?, pll prescaler) 00000 = input/2 (default) 00001 = input/3 ? ? ? 11111 = input/33 note 1: this bit is cleared when the roi bit is set and an interrupt occurs.
? 2007 microchip technology inc. preliminary ds-70289a-page 87 PIC24HJ32GP202/204 and pic24hj16gp304 register 7-3: pllfbd: pll feedback divisor register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 (1) ? ? ? ? ? ? ?plldiv<8> bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 plldiv<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8-0 plldiv<8:0>: pll feedback divisor bits (also denoted as ?m?, pll multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 ? ? ? 000110000 = 50 (default) ? ? ? 111111111 = 513
PIC24HJ32GP202/204 and pic24hj16gp304 ds-70289a-page 88 preliminary ? 2007 microchip technology inc. register 7-4: osctun: frc oscillator tuning register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frc oscillator tuning bits 011111 = center frequency + 11.625% 011110 = center frequency + 11.25% (8.23 mhz) ? ? ? 000001 = center frequency + 0.375% (7.40 mhz) 000000 = center frequency (7.37 mhz nominal) 111111 = center frequency ? 0.375% (7.345 mhz) ? ? ? 100001 = center frequency ? 11.625% (6.52 mhz) 100000 = center frequency ? 12% (6.49 mhz)
? 2007 microchip technology inc. preliminary ds-70289a-page 89 PIC24HJ32GP202/204 and pic24hj16gp304 7.2 clock switching operation applications are free to switch among any of the four clock sources (primary, lp, frc and lprc) under software control at any time. to limit the possible side effects of this flexibility, PIC24HJ32GP202/204 and pic24hj16gp304 devices have a safeguard lock built into the switch process. 7.2.1 enabling clock switching to enable clock switching, the fcksm1 configuration bit in the configuration register must be programmed to ? 0 ?. (refer to section 18.1 ?configuration bits? for further details.) if the fcksm1 configuration bit is unprogrammed (? 1 ?), the clock switching function and fail-safe clock monitor function are disabled. this is the default setting. the nosc control bits (osccon<10:8>) do not control the clock selection when clock switching is disabled. however, the cosc bits (osccon<14:12>) reflect the clock source selected by the fnosc configuration bits. the oswen control bit (osccon<0>) has no effect when clock switching is disabled. it is held at ? 0 ? at all times. 7.2.2 oscillator switching sequence performing a clock switch requires the following basic sequence: 1. read the cosc bits (osccon<14:12>) to determine the current oscillator source, if desired. 2. perform the unlock sequence to allow a write to the osccon register high byte. 3. write the appropriate value to the nosc control bits (osccon<10:8>) for the new oscillator source. 4. perform the unlock sequence to allow a write to the osccon register low byte. 5. set the oswen bit to initiate the oscillator switch. once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. the clock switching hardware compares the cosc status bits with the new value of the nosc control bits. if both of them are the same, the clock switch is a redundant operation. in this case, the oswen bit is cleared automatically and the clock switch is aborted. 2. if a valid clock switch has been initiated, the lock (osccon<5>) and the cf (osccon<3>) status bits are cleared. 3. the new oscillator is turned on by the hardware if it is not currently running. if a crystal oscillator has to be turned on, the hardware waits until the oscillator start-up timer (ost) expires. if the new source is using the pll, the hardware waits until a pll lock is detected (lock = 1 ). 4. the hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. 5. the hardware clears the oswen bit to indicate a successful clock transition. in addition, the nosc bit values are transferred to the cosc status bits. 6. the old clock source is turned off at this time, with the exception of lprc (if wdt or fscm are enabled) or lp (if lposcen remains set). 7.3 fail-safe clock monitor (fscm) the fail-safe clock monitor (fscm) allows the device to continue to operate even in the event of an oscillator failure. the fscm function is enabled by programming. if the fscm function is enabled, the lprc internal oscillator runs at all times (except during sleep mode) and is not subject to control by the watchdog timer. in the event of an oscillator failure, the fscm generates a clock failure trap event and switches the system clock over to the frc oscillator. then the application program can either attempt to restart the oscillator or execute a controlled shutdown. the trap can be treated as a warm reset by simply loading the reset address into the oscillator fail trap vector. if the pll multiplier is used to scale the system clock, the internal frc is also multiplied by the same factor on clock failure. essentially, the device switches to frc with pll on a clock failure. note: primary oscillator mode has three different submodes (xt, hs and ec), which are determined by the poscmd<1:0> config- uration bits. while an application can switch to and from primary oscillator mode in software, it cannot switch among the different primary submodes without reprogramming the device. note 1: the processor continues to execute code throughout the clock switching sequence. timing-sensitive code should not be executed during this time. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the application must switch to frc mode as a transition clock source between the two pll modes.
PIC24HJ32GP202/204 and pic24hj16gp304 ds-70289a-page 90 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70289a-page 91 PIC24HJ32GP202/204 and pic24hj16gp304 8.0 power-saving features the PIC24HJ32GP202/204 and pic24hj16gp304 devices provide the ability to manage power consump- tion by selectively managing clocking to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of circuits being clocked con- stitutes lower consumed power. PIC24HJ32GP202/ 204 and pic24hj16gp304 devices can manage power consumption in four different ways: ? clock frequency ? instruction-based sleep and idle modes ? software-controlled doze mode ? selective peripheral control in software combinations of the above methods can be used to selectively customize an application?s power consump- tion while still maintaining critical application features, such as timing-sensitive communications. 8.1 clock frequency and clock switching PIC24HJ32GP202/204 and pic24hj16gp304 devices allow a wide range of clock frequencies to be selected under application control. if the system clock configura- tion is not locked, users can choose low-power or high- precision oscillators by simply changing the nosc bits (osccon<10:8>). the process of changing a system clock during operation, as well as limitations to the pro- cess, are discussed in more detail in section 7.0 ?oscillator configuration? . 8.2 instruction-based power-saving modes PIC24HJ32GP202/204 and pic24hj16gp304 devices have two special power-saving modes that are entered through the execution of a special pwrsav instruction. sleep mode stops clock operation and halts all code execution. idle mode halts the cpu and code execu- tion, but allows peripheral modules to continue opera- tion. example 8-1 shows the assembler syntax of the pwrsav instruction. sleep and idle modes can be exited as a result of an enabled interrupt, wdt time-out or a device reset. when the device exits these modes, it is said to wake-up. 8.2.1 sleep mode in the sleep mode, ? the system clock source is shut down. if an on- chip oscillator is used, it is turned off. ? the device current consumption is reduced to a minimum, provided that no i/o pin is sourcing current. ? the fail-safe clock monitor does not operate, since the system clock source is disabled. ? the lprc clock continues to run if the wdt is enabled. ? the wdt, if enabled, is automatically cleared prior to entering sleep mode. ? some device features or peripherals may continue to operate. this includes items such as the input change notification on the i/o ports, or peripherals that use an external clock input. ? any peripheral that requires the system clock source for its operation is disabled. the device will wake-up from sleep mode on any of these events: ? any interrupt source that is individually enabled ? any form of device reset ? a wdt time-out on wake-up from sleep mode, the processor restarts with the same clock source that was active when sleep mode was entered. example 8-1: pwrsav instruction syntax note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . note: sleep_mode and idle_mode are constants defined in the assembler include file for the selected device. pwrsav #sleep_mode ; put the device into sleep mode pwrsav #idle_mode ; put the device into idle mode
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 92 preliminary ? 2007 microchip technology inc. 8.2.2 idle mode the following occur in idle mode: ? the cpu stops executing instructions. ? the wdt is automatically cleared. ? the system clock source remains active. by default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see section 8.4 ?peripheral module disable? ). ? if the wdt or fscm is enabled, the lprc also remains active. the device will wake from idle mode on any of these events: ? any interrupt that is individually enabled. ? any device reset ? a wdt time-out on wake-up from idle mode, the clock is reapplied to the cpu and instruction execution begins immediately, starting with the instruction following the pwrsav instruction, or the first instruction in the isr. 8.2.3 interrupts coincident with power save instructions any interrupt that coincides with the execution of a pwrsav instruction is held off until entry into sleep or idle mode is completed. the device then wakes up from sleep or idle mode. 8.3 doze mode the preferred strategies for reducing power consump- tion are changing clock speed and invoking one of the power-saving modes. in some circumstances, how- ever, these are not practical. for example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. reducing system clock speed can intro- duce communication errors, while using a power-sav- ing mode can stop communications completely. doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. in this mode, the system clock contin- ues to operate from the same source and at the same speed. peripheral modules continue to be clocked at the same speed, while the cpu clock speed is reduced. synchronization between the two clock domains is maintained, allowing the peripherals to access the sfrs while the cpu executes code at a slower rate. doze mode is enabled by setting the dozen bit (clkdiv<11>). the ratio between peripheral and core clock speed is determined by the doze<2:0> bits (clkdiv<14:12>). there are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default setting. programs can use doze mode to selectively reduce power consumption in event-driven applications. this allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the cpu idles, waiting for something to invoke an inter- rupt routine. an automatic return to full-speed cpu operation on interrupts can be enabled by setting the roi bit (clkdiv<15>). by default, interrupt events have no effect on doze mode operation. for example, suppose the device is operating at 20 mips and the can module has been configured for 500 kbps based on this device operating speed. if the device is placed in doze mode with a clock frequency ratio of 1:4, the can module continues to communicate at the required bit rate of 500 kbps, but the cpu now starts executing instructions at a frequency of 5 mips. 8.4 peripheral module disable the peripheral module disable (pmd) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. when a peripheral is disabled using the appropriate pmd control bit, the peripheral is in a minimum power consumption state. the control and status registers associated with the peripheral are also disabled. so writes to those registers will have no effect and read values will be invalid. a peripheral module is enabled only if both the associ- ated bit in the pmd register are cleared and the periph- eral is supported by the specific pic24h variant. if the peripheral is present in the device, it is enabled in the pmd register by default. note: if a pmd bit is set, the corresponding mod- ule is disabled after a delay of one instruc- tion cycle. similarly, if a pmd bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable mod- ule operation).
? 2007 microchip technology inc. preliminary ds70289a-page 93 PIC24HJ32GP202/204 and pic24hj16gp304 9.0 i/o ports all of the device pins (except v dd , v ss , mclr and osc1/clki) are shared among the peripherals and the parallel i/o ports. all i/o input ports feature schmitt trigger inputs for improved noise immunity. 9.1 parallel i/o (pio) ports a parallel i/o port that shares a pin with a peripheral is generally subservient to the peripheral. the peripheral?s output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the i/o pin. the logic also prevents ?loop through,? in which a port?s digital output can drive the input of a peripheral that shares the same pin. figure 9-1 shows how ports are shared with other peripherals and the associated i/o pin to which they are connected. when a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. the i/o pin can be read, but the output driver for the parallel port bit is disabled. if a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port. all port pins have three registers directly associated with their operation as digital i/o. the data direction register (trisx) determines whether the pin is an input or an output. if the data direction bit is ? 1 ?, then the pin is an input. all port pins are defined as inputs after a reset. reads from the latch (latx) read the latch. writes to the latch, write the latch. reads from the port (portx) read the port pins, while writes to the port pins write the latch. any bit and its associated data and control registers that are not valid for a particular device will be disabled. this means that the corresponding latx and trisx registers and the port pin will read as zeros. when a pin is shared with another peripheral or func- tion that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. figure 9-1: block diag ram of a typical shared port structure note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . q d ck wr lat + tris latch i/o pin wr port data bus q d ck data latch read port read tris 1 0 1 0 wr tris peripheral output data output enable peripheral input data i/o peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable read lat
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 94 preliminary ? 2007 microchip technology inc. 9.1.1 open-drain configuration in addition to the port, lat and tris registers for data control, each port pin can also be individually con- figured for either digital or open-drain output. this is controlled by the open-drain control register, odcx, associated with each port. setting any of the bits con- figures the corresponding pin to act as an open-drain output. the open-drain feature allows the generation of outputs higher than v dd (e.g., 5v) on any desired digi- tal-only pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification. 9.2 configuring analog port pins the ad1pcfg and tris registers control the opera- tion of the analog-to-digital (a/d) port pins. the port pins that are desired as analog inputs must have their corresponding tris bit set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. when the port register is read, all pins configured as analog input channels will read as cleared (a low level). pins configured as digital inputs will not convert an analog input. analog levels on any pin that is defined as a digital input (including the anx pins) can cause the input buffer to consume current that exceeds the device specifications. 9.2.1 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically this instruction would be a nop . an example is shown in example 9- 1: ?port write/read example? . 9.3 input change notification the input change notification function of the i/o ports allows the PIC24HJ32GP202/204 and pic24hj16gp304 devices to generate interrupt requests to the processor in response to a change-of- state on selected input pins. this feature can detect input change-of-states even in sleep mode, when the clocks are disabled. depending on the device pin count, up to 31 external signals (cnx pin) can be selected (enabled) for generating an interrupt request on a change-of-state. four control registers are associated with the cn mod- ule. the cnen1 and cnen2 registers contain the interrupt enable control bits for each of the cn input pins. setting any of these bits enables a cn interrupt for the corresponding pins. each cn pin also has a weak pull-up connected to it. the pull-ups act as a current source connected to the pin, and eliminate the need for external resistors when push button or keypad devices are connected. the pull-ups are enabled separately using the cnpu1 and cnpu2 registers, which contain the control bits for each of the cn pins. setting any of the control bits enables the weak pull-ups for the corresponding pins. example 9-1: port write/read example note: pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. mov 0xff00, w0 ; configure portb<15:8> as inputs mov w0, trisbb ; and portb<7:0> as outputs nop ; delay 1 cycle btss portb, #13 ; next instruction
? 2007 microchip technology inc. preliminary ds70289a-page 95 PIC24HJ32GP202/204 and pic24hj16gp304 9.4 peripheral pin select a major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on i/o pins. the challenge is even greater on low-pin count devices. in an application where more than one peripheral must be assigned to a single pin, inconve- nient workarounds in application code or a complete redesign may be the only option. peripheral pin select configuration enables peripheral set selection and placement on a wide range of i/o pins. by increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. the peripheral pin select configuration feature operates over a fixed subset of digital i/o pins. pro- grammers can independently map the input and/or out- put of most digital peripherals to any one of these i/o pins. peripheral pin select is performed in software, and generally does not require the device to be reprogrammed. hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping, once it has been established. 9.4.1 available pins the peripheral pin select feature is used with a range of up to 26 pins. the number of available pins depends on the particular device and its pin count. pins that support the peripheral pin select feature include the designation ?rpn? in their full pin designation, where ?rp? designates a remappable peripheral and ?n? is the remappable pin number. 9.4.2 available peripherals the peripheral pin select feature manages all digital- only peripherals. these include: ? general serial communications (uart and spi) ? general-purpose timer clock inputs ? timer-related peripherals (input capture and out- put compare) ? interrupt-on-change inputs. in comparison, some digital-only peripheral modules are never included in the peripheral pin select feature. this is because the peripheral?s function requires spe- cial i/o circuitry on a specific port and cannot be easily connected to multiple pins. these modules include i 2 c. a similar requirement excludes all modules with analog inputs, such as the analog-to-digital converter (adc). remappable peripherals are not associated with a default i/o pin. the peripheral must always be assigned to a specific i/o pin before it can be used. in contrast, non remappable peripherals are always avail- able on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. 9.4.2.1 peripheral pin select function priority when a remappable peripheral is active on a given i/o pin, it takes priority over all other digital i/o and digital communication peripherals associated with the pin. priority is given regardless of the type of peripheral that is mapped. remappable peripherals never take priority over any analog functions associated with the pin. 9.4.3 controlling peripheral pin select peripheral pin select features are controlled through two sets of special function registers to map peripher- als and to map outputs. since they are separately controlled, a particular peripheral?s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. the association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. 9.4.3.1 input mapping the inputs of the peripheral pin select options are mapped on the basis of the peripheral. a control regis- ter associated with a peripheral dictates the pin it will be mapped to. the rpinrx registers are used to config- ure peripheral input mapping (see register 9-1 through register 9-9). each register contains sets of 5-bit fields, with each set associated with one of the remap- pable peripherals. programming a given peripheral?s bit field with an appropriate 5-bit value maps the rpn pin with that value to that peripheral. for any given device, the valid range of values for any bit field corre- sponds to the maximum number of peripheral pin selections supported by the device. figure 9-2 illustrates remappable pin selection for u1rx input.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 96 preliminary ? 2007 microchip technology inc. figure 9-2: remappable mux input for u1rx table 9-1: remappable peripheral inputs (1) rp0 rp1 rp2 rp 25 0 25 1 2 u1rx input u1rxr[4:0] to peripheral input name function name register configuration bits external interrupt 1 int1 rpinr0 int1r[4:0] external interrupt 2 int2 rpinr1 int2r[4:0] timer 2 external clock t2ck rpinr3 t2ckr[4:0] timer 3 external clock t3ck rpinr3 t3ckr[4:0] input capture 1 ic1 rpinr7 ic1r[4:0] input capture 2 ic2 rpinr7 ic2r[4:0] input capture 7 ic7 rpinr10 ic7r[4:0] input capture 8 ic8 rpinr10 ic8r[4:0] output compare fault a ocfa rpinr11 ocfar[4:0] uart 1 receive u1rx rpinr18 u1rxr[4:0] uart 1 clear to send u1cts rpinr18 u1ctsr[4:0] spi 1 data input sdi1 rpinr20 sdi1r[4:0] spi 1 clock input sck1in rpinr20 sck1r[4:0] spi 1 slave select input ss1in rpinr21 ss1r[4:0] note 1: unless otherwise noted, all inputs use the schmitt input buffers.
? 2007 microchip technology inc. preliminary ds70289a-page 97 PIC24HJ32GP202/204 and pic24hj16gp304 9.4.3.2 output mapping in contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. in this case, a control register associated with a particular pin dictates the peripheral output to be mapped. the rporx registers are used to control output mapping. like the rpinrx registers, each register contains sets of 5-bit fields, with each set associated with one rpn pin (see register 9-10 through register 9-22). the value of the bit field corresponds to one of the periph- erals, and that peripheral?s output is mapped to the pin (see table 9-2 and figure 9-3). the list of peripherals for output mapping also includes a null value of 00000 because of the mapping tech- nique. this permits any given pin to remain unconnected from the output of any of the pin select- able peripherals. figure 9-3: multiplexing of remappable output for rpn table 9-2: output selection for remappable pin (rpn) 0 19 3 rpnr[4:0] default u1tx output enable u1rts output enable 4 18 oc1 output enable 0 19 3 default u1tx output u1rts output 4 oc2 output 18 oc1 output output enable output data rpn oc2 output enable function rpnr<4:0> output name null 00000 rpn tied to default port pin u1tx 00011 rpn tied to uart 1 transmit u1rts 00100 rpn tied to uart 1 ready to send sdo1 00111 rpn tied to spi 1 data output sck1out 01000 rpn tied to spi 1 clock output ss1out 01001 rpn tied to spi 1 slave select output oc1 10010 rpn tied to output compare 1 oc2 10011 rpn tied to output compare 2
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 98 preliminary ? 2007 microchip technology inc. 9.4.3.3 mapping the control schema of peripheral select pins is not lim- ited to a small range of fixed peripheral configurations. there are no mutual or hardware-enforced lockouts between any of the peripheral mapping sfrs. literally any combination of peripheral mappings across any or all of the rpn pins is possible. this includes both many-to-one and one-to-many mappings of peripheral inputs and outputs to pins. while such mappings may be technically possible from a configuration point of view, they may not be support- able electrically. 9.4.4 controlling configuration changes because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. pic24h devices include three features to prevent alterations to the peripheral map: ? control register lock sequence ? continuous state monitoring ? configuration bit pin select lock 9.4.4.1 control register lock under normal operation, writes to the rpinrx and rporx registers are not allowed. attempted writes appear to execute normally, but the contents of the reg- isters remain unchanged. to change these registers, they must be unlocked in hardware. the register lock is controlled by the iolock bit (osccon<6>). setting iolock prevents writes to the control registers; clear- ing iolock allows writes. to set or clear iolock, a specific command sequence must be executed: 1. write 46h to osccon<7:0>. 2. write 57h to osccon<7:0>. 3. clear (or set) iolock as a single operation. unlike the similar sequence with the oscillator?s lock bit, iolock remains in one state until changed. this allows all the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. 9.4.4.2 continuous state monitoring in addition to being protected from direct writes, the contents of the rpinrx and rporx registers are constantly monitored in hardware by shadow registers. if an unexpected change in any of the registers occurs (such as cell disturbances caused by esd or other external events), a configuration mismatch reset will be triggered. 9.4.4.3 configuration bit pin select lock as an additional level of safety, the device can be con- figured to prevent more than one write session to the rpinrx and rporx registers. the iol1way (fosc) configuration bit blocks the iolock bit from being cleared after it has been set once. in the default (unprogrammed) state, iol1way is set restricting the users to one write session. programming iol1way allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. 9.4.5 considerations for peripheral pin selection the ability to control peripheral pin selection introduces several considerations into application design, includ- ing several common peripherals that are only available as remappable peripherals. 9.4.5.1 configuration the peripheral pin selects are not available on default pins in the device?s default (reset) state. more specifi- cally, since all rpinrx and rporx registers reset to 0000h , this means all peripheral pin select inputs are tied to rp0, while all peripheral pin select outputs are disconnected. this means that before any other appli- cation code is executed, the user application must ini- tialize the device with the proper peripheral configuration. since the iolock bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has come out of reset. for the sake of applica- tion safety, however, it is always a good idea to set iolock and lock the configuration after writing to the control registers. because the unlock sequence is timing-critical, it must be executed as an assembly-language routine, in the same manner as changes to the oscillator configuration. if the bulk of the application is written in c or another high-level language, the unlock sequence should be performed by writing inline assembly. note: mplab ? c30 provides built-in c language functions for unlocking the osccon register: __builtin_write_oscconl(value) __builtin_write_oscconh(value) see mplab help for more information.
? 2007 microchip technology inc. preliminary ds70289a-page 99 PIC24HJ32GP202/204 and pic24hj16gp304 9.4.5.2 changing the configuration choosing the configuration requires review of all peripheral pin selects and their pin assignments, especially those that will not be used in the application. in all cases, unused pin selectable peripherals should be disabled completely. unused peripherals should have their inputs assigned to an unused rpn pin function. i/o pins with unused rpn functions should be configured with the null peripheral output. the assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin?s i/o circuitry. this means adding a pin selectable output to a pin can inadvertently drive an existing peripheral input when the output is driven. program- mers must be familiar with the behavior of other fixed peripherals that share a remappable pin, and know when to enable or disable them. to be safe, fixed digi- tal peripherals that share the same pin should be dis- abled when not in use. 9.4.5.3 pin operation configuring a remappable pin for a specific peripheral does not automatically turn that feature on. the periph- eral must be specifically configured for an operation and enabled, as if it were tied to a fixed pin. where this happens in the application code (immediately following device reset and peripheral configuration, or inside the main application routine) depends on the peripheral and its use in the application. 9.4.5.4 analog function a final consideration is that peripheral pin select func- tions neither override analog inputs nor reconfigure pins with analog functions for digital i/o. if a pin is con- figured as an analog input on device reset, it must be explicitly reconfigured as digital i/o when used with a peripheral pin select. 9.4.5.5 configuration example example 9-2 shows a configuration for bidirectional communication with flow control using uart1. the fol- lowing input and output functions are used: ? input functions: u1rx, u1cts ? output functions: u1tx, u1rts 9.5 peripheral pin select registers the PIC24HJ32GP202/204 and pic24hj16gp304 devices implement 17 registers for remappable periph- eral configuration: ? input remappable peripheral registers (9) ? output remappable peripheral registers (8) example 9-2: conf iguring uart1 input and output functions note: input and output register values can only be changed if osccon[iolock] = 0 . see section 9.4.4.1 ?control register lock? for a specific command sequence. //************************************* // unlock registers //************************************* asm volatile ( "mov #oscconl, w1 \n" "mov #0x46, w2 \n" "mov #0x57, w3 \n" "mov.b w2, [w1] \n" "mov.b w3, [w1] \n" "bclr osccon, 6"); //*************************** // configure input functions // (see table 9-1) //*************************** //*************************** // assign u1rx to pin rp0 //*************************** rpinr18bits.u1rxr = 0; //*************************** // assign u1cts to pin rp1 //*************************** rpinr18bits.u1ctsr = 1; //*************************** // configure output functions // (see table 9-2) //*************************** //*************************** // assign u1tx to pin rp2 //*************************** rpor1bits.rp2r = 3; //*************************** // assign u1rts to pin rp3 //*************************** rpor1bits.rp3r = 4; //************************************* // lock registers //************************************* asm volatile ( "mov #oscconl, w1 \n" "mov #0x46, w2 \n" "mov #0x57, w3 \n" "mov.b w2, [w1] \n" "mov.b w3, [w1] \n" "bset osccon, 6");
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 100 preliminary ? 2007 microchip technology inc. register 9-1: rpinr0: peripheral pin select input register 0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?int1r<4:0> bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 int1r<4:0>: assign external interrupt 1 (intr1) to the corresponding rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-0 unimplemented: read as ? 0 ?
? 2007 microchip technology inc. preliminary ds70289a-page 101 PIC24HJ32GP202/204 and pic24hj16gp304 register 9-2: rpinr1: peripheral pin select input register 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?int2r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 int2r<4:0>: assign external interrupt 2 (intr2) to the corresponding rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 102 preliminary ? 2007 microchip technology inc. register 9-3: rpinr3: peripheral pin select input register 3 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?t3ckr<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?t2ckr<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 t3ckr<4:0>: assign timer3 external clock (t3ck) to the corresponding rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 t2ckr<4:0>: assign timer2 external clock (t2ck) to the corresponding rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0
? 2007 microchip technology inc. preliminary ds70289a-page 103 PIC24HJ32GP202/204 and pic24hj16gp304 register 9-4: rpinr7: peripheral pin select input register 7 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ic2r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ic1r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 ic2r<4:0>: assign input capture 2 (ic2) to the corresponding rpn pin t2ckr<4:0>: assign timer2 external clock (t2ck) to the corresponding rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 ic1r<4:0>: assign input capture 1 (ic1) to the corresponding rpn pin t2ckr<4:0>: assign timer2 external clock (t2ck) to the corresponding rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 104 preliminary ? 2007 microchip technology inc. register 9-5: rpir10: peripheral pin select input registers 10 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ic8r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ic7r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 ic8r<4:0>: assign input capture 8 (ic8) to the corresponding pin rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 ic7r<4:0>: assign input capture 7 (ic7) to the corresponding pin rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0
? 2007 microchip technology inc. preliminary ds70289a-page 105 PIC24HJ32GP202/204 and pic24hj16gp304 register 9-6: rpinr11: peripheral pin select input register 11 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?ocfar<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 ocfar<4:0>: assign output capture a (ocfa) to the corresponding rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 106 preliminary ? 2007 microchip technology inc. register 9-7: rpinr18: peripheral pin select input register 18 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? u1ctsr<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?u1rxr<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 u1ctsr<4:0>: assign uart 1 clear to send (u1cts ) to the corresponding rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 u1rxr<4:0>: assign uart 1 receive (u1rx) to the corresponding rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0
? 2007 microchip technology inc. preliminary ds70289a-page 107 PIC24HJ32GP202/204 and pic24hj16gp304 register 9-8: rpinr20: peripheral pin select input register 20 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?sck1r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?sdi1r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 sck1r<4:0>: assign spi 1 clock input (sck1in) to the corresponding rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 sdi1r<4:0>: assign spi 1 data input (sdi1) to the corresponding rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 108 preliminary ? 2007 microchip technology inc. register 9-9: rpinr21: peripheral pin select input register 21 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ss1r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 ss1r<4:0>: assign spi1 slave select input (ss1in) to the corresponding rpn pin 11111 = input tied to vss 11001 = input tied to rp25 ? ? ? 00001 = input tied to rp1 00000 = input tied to rp0
? 2007 microchip technology inc. preliminary ds70289a-page 109 PIC24HJ32GP202/204 and pic24hj16gp304 register 9-10: rpor0: peripheral pin select output registers 0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp1r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp0r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp1r<4:0>: peripheral output function is assigned to rp1 output pin (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp0r<4:0>: peripheral output function is assigned to rp0 output pin (see table 9-2 for peripheral function numbers) register 9-11: rpor1: peripheral pin select output registers 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp3r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp2r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp3r<4:0>: peripheral output function is assigned to rp3 output pin (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp2r<4:0>: peripheral output function is assigned to rp2 output pin (see table 9-2 for peripheral function numbers)
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 110 preliminary ? 2007 microchip technology inc. register 9-12: rpor2: peripheral pin select output registers 2 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp5r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp4r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp5r<4:0>: peripheral output function is assigned to rp5 output pin (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp4r<4:0>: peripheral output function is assigned to rp4 output pin (see table 9-2 for peripheral function numbers) register 9-13: rpor3: peripheral pin select output registers 3 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp7r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp6r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp7r<4:0>: peripheral output function is assigned to rp7 output pin (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp6r<4:0>: peripheral output function is assigned to rp6 output pin (see table 9-2 for peripheral function numbers)
? 2007 microchip technology inc. preliminary ds70289a-page 111 PIC24HJ32GP202/204 and pic24hj16gp304 register 9-14: rpor4: peripheral pin select output registers 0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp9r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp8r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp9r<4:0>: peripheral output function is assigned to rp9 output pin (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp8r<4:0>: peripheral output function is assigned to rp8 output pin (see table 9-2 for peripheral function numbers) register 9-15: rpor5: peripheral pin select output registers 5 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp11r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp10r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp11r<4:0>: peripheral output function is assigned to rp11 output pin (see table 9-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp10r<4:0>: peripheral output function is assigned to rp10 output pin (see table 9-2 for periph- eral function numbers)
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 112 preliminary ? 2007 microchip technology inc. register 9-16: rpor6: peripheral pin select output registers 6 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp13r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp12r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp13r<4:0>: peripheral output function is assigned to rp13 output pin (see table 9-2 for periph- eral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp12r<4:0>: peripheral output function is assigned to rp12 output pin (see table 9-2 for periph- eral function numbers) register 9-17: rpor7: peripheral pin select output registers 7 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp15r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp14r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp15r<4:0>: peripheral output function is assigned to rp15 output pin (see table 9-2 for periph- eral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp14r<4:0>: peripheral output function is assigned to rp14 output pin (see table 9-2 for periph- eral function numbers)
? 2007 microchip technology inc. preliminary ds70289a-page 113 PIC24HJ32GP202/204 and pic24hj16gp304 register 9-18: rpor7: peripheral pin select output registers 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp17r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp16r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp15r<4:0>: peripheral output function is assigned to rp15 output pin (see table 9-2 for periph- eral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp14r<4:0>: peripheral output function is assigned to rp14 output pin (see table 9-2 for periph- eral function numbers) register 9-19: rpor7: peripheral pin select output registers 9 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp19r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp18r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp19r<4:0>: peripheral output function is assigned to rp19 output pin (see table 9-2 for periph- eral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp18r<4:0>: peripheral output function is assigned to rp18 output pin (see table 9-2 for periph- eral function numbers)
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 114 preliminary ? 2007 microchip technology inc. register 9-20: rpor7: peripheral pin select output registers 10 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp21r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp20r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp21r<4:0>: peripheral output function is assigned to rp21 output pin (see table 9-2 for periph- eral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp20r<4:0>: peripheral output function is assigned to rp20 output pin (see table 9-2 for periph- eral function numbers) register 9-21: rpor7: peripheral pin select output registers 11 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp23r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp22r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp23r<4:0>: peripheral output function is assigned to rp23 output pin (see table 9-2 for periph- eral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp22r<4:0>: peripheral output function is assigned to rp22 output pin (see table 9-2 for periph- eral function numbers)
? 2007 microchip technology inc. preliminary ds70289a-page 115 PIC24HJ32GP202/204 and pic24hj16gp304 register 9-22: rpor7: peripheral pin select output registers 12 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp25r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp24r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp25r<4:0>: peripheral output function is assigned to rp25 output pin (see table 9-2 for periph- eral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp24r<4:0>: peripheral output function is assigned to rp24 output pin (see table 9-2 for periph- eral function numbers)
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 116 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70289a-page 117 PIC24HJ32GP202/204 and pic24hj16gp304 10.0 timer1 the timer1 module is a 16-bit timer, which can serve as the time counter for the real-time clock, or operate as a free-running interval timer/counter. timer1 can operate in three modes: ? 16-bit timer ? 16-bit synchronous counter ? 16-bit asynchronous counter timer1 also supports these features: ? timer gate operation ? selectable prescaler settings ? timer operation during cpu idle and sleep modes ? interrupt on 16-bit period register match or falling edge of external gate signal figure 10-1 shows a block diagram of the 16-bit timer module. to configure timer1 for operation: 1. set the ton bit (= 1 ) in the t1con register. 2. select the timer prescaler ratio using the tckps<1:0> bits in the t1con register. 3. set the clock and gating modes using the tcs and tgate bits in the t1con register. 4. set or clear the tsync bit in t1con to select synchronous or asynchronous operation. 5. load the timer period value into the pr1 register. 6. if interrupts are required, set the interrupt enable bit, t1ie. use the priority bits, t1ip<2:0>, to set the interrupt priority. figure 10-1: 16-bit time r1 module block diagram note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . ton sosci sosco/ pr1 set t1if equal comparator tmr1 reset soscen 1 0 tsync q qd ck tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 t1ck tcs 1x 01 tgate 00 sync gate sync
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 118 preliminary ? 2007 microchip technology inc. register 10-1: t1con: ti mer1 control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 ? tgate tckps<1:0> ? tsync tcs ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer1 on bit 1 = starts 16-bit timer1 0 = stops 16-bit timer1 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer1 gated time accumulation enable bit when t1cs = 1 : this bit is ignored. when t1cs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps<1:0> timer1 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 unimplemented: read as ? 0 ? bit 2 tsync: timer1 external clock input synchronization select bit when tcs = 1 : 1 = synchronize external clock input 0 = do not synchronize external clock input when tcs = 0 : this bit is ignored. bit 1 tcs: timer1 clock source select bit 1 = external clock from pin t1ck (on the rising edge) 0 = internal clock (f cy ) bit 0 unimplemented: read as ? 0 ?
? 2007 microchip technology inc. preliminary ds70289a-page 119 PIC24HJ32GP202/204 and pic24hj16gp304 11.0 timer2/3 feature the timer2/3 feature has 32-bit timers that can also be configured as two independent 16-bit timers with selectable operating modes. as a 32-bit timer, the timer2/3 feature permits opera- tion in three modes: ? two independent 16-bit timers (timer2 and timer3) with all 16-bit operating modes (except asynchronous counter mode) ? single 32-bit timer (timer2/3) ? single 32-bit synchronous counter (timer2/3) the timer2/3 feature also supports: ? timer gate operation ? selectable prescaler settings ? timer operation during idle and sleep modes ? interrupt on a 32-bit period register match ? time base for input capture and output compare modules (timer2 and timer3 only) ? adc1 event trigger (timer2/3 only) individually, all eight of the 16-bit timers can function as synchronous timers or counters. they also offer the features that are listed above, except for the event trig- ger. the operating modes and enabled features are determined by setting the appropriate bit(s) in the t2con and t3con registers. t2con registers are shown in generic form in register 11-1. t3con regis- ters are shown in register 11-2. for 32-bit timer/counter operation, timer2 is the least significant word, and timer3 is the most significant word of the 32-bit timers. 11.1 32-bit operation to configure the timer2/3 feature for 32-bit operation: 1. set the corresponding t32 control bit. 2. select the prescaler ratio for timer2 using the tckps<1:0> bits. 3. set the clock and gating modes using the corresponding tcs and tgate bits. 4. load the timer period value. pr3 contains the most significant word of the value, while pr2 contains the least significant word. 5. set the interrupt enable bit t3ie, if interrupts are required. use the priority bits t3ip<2:0> to set the interrupt priority. while timer2 controls the timer, the interrupt appears as a timer3 inter- rupt. 6. set the corresponding ton bit. the timer value at any point is stored in the register pair tmr3:tmr2. tmr3 always contains the most signifi- cant word of the count, while tmr2 contains the least significant word. to configure any of the timers for individual 16-bit operation: 1. clear the t32 bit corresponding to that timer. 2. select the timer prescaler ratio using the tckps<1:0> bits. 3. set the clock and gating modes using the tcs and tgate bits. 4. load the timer period value into the prx register. 5. if interrupts are required, set the interrupt enable bit, txie. use the priority bits, txip<2:0>, to set the interrupt priority. 6. set the ton bit. note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . note: for 32-bit operation, t3con control bits are ignored. only t2con control bit is used for setup and control. timer2 clock and gate inputs are used for the 32-bit timer modules, but an interrupt is gener- ated with the timer3 interrupt flags.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 120 preliminary ? 2007 microchip technology inc. figure 11-1: timer2/3 (32-bit) block diagram (1) set t3if equal comparator pr3 pr2 reset lsb msb note 1: the 32-bit timer control bit, t32, must be set for 32-bit timer/counter operation. all control bits are respective to the t2con register. 2: the adc event trigger is available only on timer2/3. data bus<15:0> tmr3hld read tmr2 write tmr2 16 16 16 q qd ck tgate 0 1 ton tckps<1:0> 2 t cy tcs 1x 01 tgate 00 t2ck adc event trigger (2) gate sync prescaler 1, 8, 64, 256 sync tmr3 tmr2 16
? 2007 microchip technology inc. preliminary ds70289a-page 121 PIC24HJ32GP202/204 and pic24hj16gp304 figure 11-2: timer2 ( 16-bit) block diagram ton tckps<1:0> prescaler 1, 8, 64, 256 2 t cy tcs tgate t2ck pr2 set t2if equal comparator tmr2 reset q qd ck tgate 1 0 gate sync 1x 01 00 sync
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 122 preliminary ? 2007 microchip technology inc. register 11-1: t2con control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 ? tgate tckps<1:0> t32 (1) ?tcs ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer2 on bit when t32 = 1 : 1 = starts 32-bit timer2/3 0 = stops 32-bit timer2/3 when t32 = 0 : 1 = starts 16-bit timer2 0 = stops 16-bit timer2 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer2 gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps<1:0>: timer2 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 t32: 32-bit timer mode select bit (1) 1 = timer2 and timer3 form a single 32-bit timer 0 = timer2 and timer3 act as two 16-bit timers bit 2 unimplemented: read as ? 0 ? bit 1 tcs: timer2 clock source select bit 1 = external clock from pin t2ck (on the rising edge) 0 = internal clock (f cy ) bit 0 unimplemented: read as ? 0 ? note 1: in 32-bit mode, t3con control bits do not affect 32-bit timer operation.
? 2007 microchip technology inc. preliminary ds70289a-page 123 PIC24HJ32GP202/204 and pic24hj16gp304 register 11-2: t3con control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton (1) ?tsidl (1) ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 ?tgate (1) tckps<1:0> (1) ? ?tcs (1) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer3 on bit (1) 1 = starts 16-bit timer3 0 = stops 16-bit timer3 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit (1) 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer3 gated time accumulation enable bit (1) when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps<1:0>: timer3 input clock prescale select bits (1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 unimplemented: read as ? 0 ? bit 1 tcs: timer3 clock source select bit (1) 1 = external clock from pin t3ck (on the rising edge) 0 = internal clock (f cy ) bit 0 unimplemented: read as ? 0 ? note 1: when 32-bit operation is enabled (t2con<3> = 1 ), these bits have no effect on timer3 operation; all timer functions are set through t2con.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 124 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds-70289a-page 125 PIC24HJ32GP202/204 and pic24hj16gp304 12.0 input capture the input capture module is useful in applications requiring frequency (period) and pulse measurement. the PIC24HJ32GP202/204 and pic24hj16gp304 devices support up to eight input capture channels. the input capture module captures the 16-bit value of the selected time base register when an event occurs at the icx pin. the events that cause a capture event are listed below in three categories: ? simple capture event modes: - capture timer value on every falling edge of input at icx pin - capture timer value on every rising edge of input at icx pin ? capture timer value on every edge (rising and falling) ? prescaler capture event modes: - capture timer value on every 4th rising edge of input at icx pin -capture timer value on every 16th rising edge of input at icx pin each input capture channel can select one of the two 16-bit timers (timer2 or timer3) for the time base. the selected timer can use either an internal or external clock. other operational features include: ? device wake-up from capture pin during cpu sleep and idle modes ? interrupt on input capture event ? four-word fifo buffer for capture values - interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled ? use of input capture to provide additional sources of external interrupts figure 12-1: input capture block diagram note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . icxbuf icx pin icm<2:0> (icxcon<2:0>) mode select 3 10 set flag icxif (in ifsn register) tmr2 tmr3 edge detection logic 16 16 fifo r/w logic icxi<1:0> icov, icbne (icxcon<4:3>) icxcon interrupt logic system bus from 16-bit timers ictmr (icxcon<7>) fifo prescaler counter (1, 4, 16) and clock synchronizer note: an ?x? in a signal, register or bit nam e denotes the number of the capture channel.
PIC24HJ32GP202/204 and pic24hj16gp304 ds-70289a-page 126 preliminary ? 2007 microchip technology inc. 12.1 input capture registers register 12-1: icxcon: input capture x control register u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?icsidl ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-0, hc r-0, hc r/w-0 r/w-0 r/w-0 ictmr ici<1:0> icov icbne icm<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 icsidl: input capture module stop in idle control bit 1 = input capture module will halt in cpu idle mode 0 = input capture module will continue to operate in cpu idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7 ictmr: input capture timer select bits 1 = tmr2 contents are captured on capture event 0 = tmr3 contents are captured on capture event bit 6-5 ici<1:0>: select number of captures per interrupt bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture overflow status flag bit (read-only) 1 = input capture overflow occurred 0 = no input capture overflow occurred bit 3 icbne: input capture buffer empty status bit (read-only) 1 = input capture buffer is not empty, at least one more capture value can be read 0 = input capture buffer is empty bit 2-0 icm<2:0>: input capture mode select bits 111 =input capture functions as interrupt pin only when device is in sleep or idle mode (rising edge detect only, all other control bits are not applicable.) 110 =unused (module disabled) 101 =capture mode, every 16th rising edge 100 =capture mode, every 4th rising edge 011 =capture mode, every rising edge 010 =capture mode, every falling edge 001 =capture mode, every edge (rising and falling) (ici<1:0> bits do not control interrupt generation for this mode.) 000 =input capture module turned off
? 2007 microchip technology inc. preliminary ds70289a-page 127 PIC24HJ32GP202/204 and pic24hj16gp304 13.0 output compare 13.1 setup for single output pulse generation when the ocm control bits (ocxcon<2:0>) are set to ? 100 ?, the selected output compare channel initializes the ocx pin to the low state and generates a single output pulse. to generate a single output pulse, the following steps are required. these steps assume timer source is initially turned off though this is not a requirement for the module operation. 1. determine the instruction clock cycle time. take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. calculate time to the rising edge of the output pulse relative to the tmry start value (0000h). 3. calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. 4. write the value computed in step 2 into the output compare register, ocxr, and the value computed in step 3 into the output compare secondary reg- ister, ocxrs. 5. set timer period register, pry, to a value equal to or greater than value in ocxrs, the output compare secondary register. 6. set the ocm bits to ? 100 ? and the octsel (ocxcon<3>) bit to the desired timer source. the ocx pin state will now be driven low. 7. set the ton (tycon<15>) bit to ? 1 ?, which enables the compare time base to count. upon the first match between tmry and ocxr, the ocx pin will be driven high. when the incrementing timer, tmry, matches the output compare secondary register, ocxrs, the second and trailing edge (high-to-low) of the pulse is driven onto the ocx pin. no additional pulses are driven onto the ocx pin and it remains at low. as a result of the second compare match event, the ocxif interrupt flag bit is set. this results in an interrupt if it is enabled by setting the ocxie bit. for further information on peripheral interrupts, refer to section 6.0 ?interrupt controller? . 8. change the timer and compare register settings to initiate another single pulse output, if needed; and then issue a write to set the ocm bits to ? 100 ?. disabling and re-enabling the timer, and clearing the tmry register, are not required, but may be advantageous for defining a pulse from a known event time boundary. the output compare module does not have to be disabled after the falling edge of the output pulse. another pulse can be initiated by rewriting the value of the ocxcon register. 13.2 setup for continuous output pulse generation when the ocm control bits (ocxcon<2:0>) are set to ? 101 ?, the selected output compare channel initializes the ocx pin to the low state and generates output pulses on each and every compare match event. to configure the module to generate a continuous stream of output pulses, the following steps are required. these steps assume that the timer source is initially turned off but this is not a requirement for the module operation. 1. determine the instruction clock cycle time. take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. calculate time to the rising edge of the output pulse relative to the tmry start value (0000h). 3. calculate the time to the falling edge of the pulse, based on the desired pulse width and the time to the rising edge of the pulse. 4. write the values computed in step 2 into the out- put compare register, ocxr, and value computed in step 3 into the output compare secondary reg- ister, ocxrs. 5. set timer period register, pry, to a value equal to or greater than value in ocxrs, the output compare secondary register. 6. set the ocm bits to ? 101 ? and the octsel bit to the desired timer source. the ocx pin state will now be driven low. 7. enable the compare time base by setting the ton (tycon<15>) bit to ? 1 ?. upon the first match between tmry and ocxr, the ocx pin will be driven high. when the compare time base, tmry, matches the output compare secondary register, ocxrs, the second and trailing edge (high-to-low) of the pulse is driven onto the ocx pin. 8. as a result of the second compare match event, the ocxif interrupt flag bit is set. when the compare time base and the value in its respective timer period register match, the tmry register resets to 0x0000 and resumes counting. 9. steps 8 through 11 are repeated and a continuous stream of pulses is generated, indefinitely. the ocxif flag is set on each ocxrs-tmry compare match event. note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? .
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 128 preliminary ? 2007 microchip technology inc. 13.3 pulse-width modulation mode use the following steps when configuring the output compare module for pwm operation: 1. set the pwm period by writing to the selected timer period register (pry). 2. set the pwm duty cycle by writing to the ocxrs register. 3. write the oxcr register with the initial duty cycle. 4. enable interrupts, if required, for the timer and output compare modules. the output compare interrupt is required for pwm fault pin utilization. 5. configure the output compare module for one of the two pwm operation modes by writing to the output compare mode bits, ocm<2:0> and (ocxcon<2:0>). 6. set the tmry prescale value and enable the time base by setting ton = 1 (txcon<15>) 13.3.1 pwm period the pwm period is specified by writing to pry, the timer period register. the pwm period can be calculated using equation 13-1: equation 13-1: calculating the pwm period 13.3.2 pwm duty cycle specify the pwm duty cycle by writing to the ocxrs register. the ocxrs register can be written to at any time, but the duty cycle value is not latched into ocxr until a match between pry and tmry occurs (i.e., the period is complete). this provides a double buffer for the pwm duty cycle and is essential for glitchless pwm operation. in the pwm mode, ocxr is a read-only reg- ister. some important boundary parameters of the pwm duty cycle include: ? if the output compare register, ocxr, is loaded with 0000h, the ocx pin will remain low (0% duty cycle). ? if ocxr is greater than pry (timer period register), the pin will remain high (100% duty cycle). ? if ocxr is equal to pry, the ocx pin will be low for one time base count value and high for all other count values. see example 13-1 for pwm mode timing details. table 13-1 shows an example of pwm frequencies and resolutions for a device operating at 10 mips. equation 13-2: calculation fo r maximum pwm resolution note: the ocxr register should be initialized before the output compare module is first enabled. the ocxr register becomes a read-only duty cycle register when the module is operated in the pwm modes. the value held in ocxr will become the pwm duty cycle for the first pwm period. the contents of the output compare secondary register, ocxrs, will not be transferred into ocxr until a time base period match occurs. note: a pry value of n will produce a pwm period of n + 1 time base count cycles. for example, a value of 7 written into the pry register will yield a period consisting of eight time base cycles. pwm period = [(pry) + 1] ? t cy ? (timer prescale value) pwm frequency = 1/[pwm period] where: ( ) maximum pwm resolution (bits) = f cy f pwm log 10 log 10 (2) bits
? 2007 microchip technology inc. preliminary ds70289a-page 129 PIC24HJ32GP202/204 and pic24hj16gp304 example 13-1: pwm period and duty cycle calculations table 13-1: example pwm frequencies and resolutions at 4 mips (f cy = 4 mhz) table 13-2: example pwm frequencies and resolutions at 16 mips (f cy = 16 mhz) table 13-3: example pwm frequencies and resolutions at 40 mips (f cy = 40 mhz) pwm frequency 7.6 hz 61 hz 122 hz 977 hz 3.9 khz 31.3 khz 125 khz timer prescaler ratio 8111111 period register value ffffh ffffh 7fffh 0fffh 03ffh 007fh 001fh resolution (bits) 16 16 15 12 10 7 5 pwm frequency 30.5 hz 244 hz 488 hz 3.9 khz 15.6 khz 125 khz 500 khz timer prescaler ratio 8111111 period register value ffffh ffffh 7fffh 0fffh 03ffh 007fh 001fh resolution (bits) 16 16 15 12 10 7 5 pwm frequency 76 hz 610 hz 1.22 hz 9.77 khz 39 khz 313 khz 1.25 mhz timer prescaler ratio 8111111 period register value ffffh ffffh 7fffh 0fffh 03ffh 007fh 001fh resolution (bits) 16 16 15 12 10 7 5 1. find the timer period register value for a desired pwm frequency that is 52.08 khz, where f cy = 16 mhz and a timer2 prescaler setting of 1:1. t cy = 62.5 ns pwm period = 1/pwm frequency = 1/52.08 khz = 19.2 ms pwm period = (pr2 + 1) ? t cy ? (timer2 prescale value) 19.2 ms = (pr2 + 1) ? 62.5 ns ? 1 pr2 = 306 2. find the maximum resolution of the duty cycle that can be us ed with a 52.08 khz frequency and a 32 mhz device clock rate: pwm resolution = log 10 (f cy /f pwm )/log 10 2) bits =(log 10 (16 mhz/52.08 khz)/log 10 2) bits = 8.3 bits
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 130 preliminary ? 2007 microchip technology inc. figure 13-1: output comp are module block diagram ocxr (1) comparator output logic ocm2:ocm0 output enable ocx (1) set flag bit ocxif (1) ocxrs (1) mode select 3 note 1: where ?x? is shown, reference is made to the registers associated with the respective output compare channels 1 through 8. 2: ocfa pin controls oc1-oc2 channels. 3: tmr2/tmr3 can be selected via octsel(ocxocn<3>) bit. octsel 0 1 16 16 ocfa tmr register inputs from time bases (3) period match signals from time bases (3) 0 1 q s r
? 2007 microchip technology inc. preliminary ds70289a-page 131 PIC24HJ32GP202/204 and pic24hj16gp304 13.4 output compare register register 13-1: ocxcon: output compare x control register u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?ocsidl ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r-0 hc r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ocflt octsel ocm<2:0> bit 7 bit 0 legend: hc = cleared in hardware hs = set in hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ocsidl: stop output compare in idle mode control bit 1 = output compare x will halt in cpu idle mode 0 = output compare x will continue to operate in cpu idle mode bit 12-5 unimplemented: read as ? 0 ? bit 4 ocflt: pwm fault condition status bit 1 = pwm fault condition has occurred (cleared in hardware only) 0 = no pwm fault condition has occurred (this bit is only used when ocm<2:0> = 111 .) bit 3 octsel: output compare timer select bit 1 = timer3 is the clock source for compare x 0 = timer2 is the clock source for compare x bit 2-0 ocm<2:0>: output compare mode select bits 111 = pwm mode on ocx, fault pin enabled 110 = pwm mode on ocx, fault pin disabled 101 = initialize ocx pin low, generate continuous output pulses on ocx pin 100 = initialize ocx pin low, generate single output pulse on ocx pin 011 = compare event toggles ocx pin 010 = initialize ocx pin high, compare event forces ocx pin low 001 = initialize ocx pin low, compare event forces ocx pin high 000 = output compare channel is disabled
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 132 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70289a-page 133 PIC24HJ32GP202/204 and pic24hj16gp304 14.0 serial peripheral interface (spi) the serial peripheral interface (spi) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices can be serial eeproms, shift registers, display drivers, analog-to-digital converters (adc) and so on. the spi module is compatible with spi and siop from motorola ? . each spi module consists of a 16-bit shift register, spixsr (where x = 1 or 2), used for shifting data in and out, and a buffer register, spixbuf. a control register, spixcon, configures the module. additionally, a status register, spixstat, indicates status conditions. the serial interface consists of 4 pins: ? sdix (serial data input) ? sdox (serial data output) ? sckx (shift clock input or output) ? ssx (active low slave select). in master mode operation, sck is a clock output. in slave mode, it is a clock input. 14.1 interrupts a series of 8 or 16 clock pulses shift out bits from the spixsr to sdox pin and simultaneously shift in data from the sdix pin. an interrupt is generated when the transfer is complete and the corresponding interrupt flag bit (spi1if) is set. this interrupt can be disabled through an interrupt enable bit (spi1ie). 14.2 receive operations the receive operation is double-buffered. when a com- plete byte is received, it is transferred from spixsr to spixbuf. if the receive buffer is full when new data is being trans- ferred from spixsr to spixbuf, the module sets the spirov bit, indicating an overflow condition. the trans- fer of the data from spixsr to spixbuf is not com- pleted, and the new data is lost. the module will not respond to scl transitions while spirov is ? 1 ?, effec- tively disabling the module until spixbuf is read by user software. 14.3 transmit operations transmit writes are also double-buffered. the user appli- cation writes to spixbuf. when the master or slave transfer is completed, the contents of the shift register (spixsr) are moved to the receive buffer. if any transmit data has been written to the buffer register, the contents of the transmit buffer are moved to spixsr. the received data is thus placed in spixbuf and the transmit data in spixsr is ready for the next transfer. 14.4 spi setup to set up the spi module for the master mode of operation: 1. if using interrupts: a) clear the spixif bit in the respective ifsn register. b) set the spixie bit in the respective iecn register. c) write the spixip bits in the respective ipcn register to set the interrupt priority. 2. write the desired settings to the spixcon register with msten (spixcon1<5>) = 1 . 3. clear the spirov bit (spixstat<6>). 4. enable spi operation by setting the spien bit (spixstat<15>). 5. write the data to be transmitted to the spixbuf register. transmission (and reception) will start as soon as data is written to the spixbuf register. to set up the spi module for the slave mode of operation: 1. clear the spixbuf register. 2. if using interrupts: a) clear the spixif bit in the respective ifsn register. b) set the spixie bit in the respective iecn register. c) write the spixip bits in the respective ipcn register to set the interrupt priority. 3. write the desired settings to the spixcon1 and spixcon2 registers with msten (spixcon1<5>) = 0 . 4. clear the smp bit. 5. if the cke bit is set, then set the ssen bit (spixcon1<7>) to enable the ssx pin. 6. clear the spirov bit (spixstat<6>). 7. enable spi operation by setting the spien bit (spixstat<15>). note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . note: both the transmit buffer (spixtxb) and the receive buffer (spixrxb) are mapped to the same register address, spixbuf. do not perform read-modify-write opera- tions (such as bit-oriented instructions) on the spixbuf register.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 134 preliminary ? 2007 microchip technology inc. the spi module generates an interrupt indicating com- pletion of a byte or word transfer, as well as a separate interrupt for all spi error conditions. figure 14-1: spi modu le block diagram internal data bus sdix sdox ssx sckx spixsr bit 0 shift control edge select f cy primary 1:1/4/16/64 enable prescaler sync spixbuf control transfer transfer write spixbuf read spixbuf 16 spixcon1<1:0> spixcon1<4:2> master clock clock control secondary prescaler 1:1 to 1:8 spixrxb spixtxb
? 2007 microchip technology inc. preliminary ds70289a-page 135 PIC24HJ32GP202/204 and pic24hj16gp304 figure 14-2: spi mast er/slave connection figure 14-3: spi master and fr ame master connection diagram figure 14-4: spi master and fr ame slave connection diagram serial receive buffer (spixrxb) lsb msb sdix sdox processor 2 (spi slave) sckx ssx (1) serial transmit buffer (spixtxb) serial receive buffer (spixrxb) shift register (spixsr) msb lsb sdox sdix processor 1 (spi master) serial clock (ssen (spixcon1<7>) = 1 and msten (spixcon1<5>) = 0 ) note 1: using the ssx pin in slave mode of operation is optional. 2: user application must write transmit data to read received data from spixbuf. the spixtxb and spixrxb registers are memory mapped to spixbuf. sckx serial transmit buffer (spixtxb) (msten (spixcon1<5>) = 1 ) spi buffer (spixbuf) (2) spi buffer (spixbuf) (2) shift register (spixsr) sdox sdix pic24h serial clock ssx sckx frame sync pulse sdix sdox processor 2 ssx sckx sdox sdix pic24h serial clock ssx sckx frame sync pulse sdix sdox processor 2 ssx sckx
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 136 preliminary ? 2007 microchip technology inc. figure 14-5: spi slave and fram e master connection diagram figure 14-6: spi slave, fram e slave connection diagram equation 14-1: relationship between device and spi clock speed table 14-1: sample sckx frequencies f cy = 40 mhz secondary prescaler settings 1:1 2:1 4:1 6:1 8:1 primary prescaler settings 1:1 invalid invalid 10000 6666.67 5000 4:1 10000 5000 2500 1666.67 1250 16:1 2500 1250 625 416.67 312.50 64:1 625 312.5 156.25 104.17 78.125 f cy = 5 mhz primary prescaler settings 1:1 5000 2500 1250 833 625 4:1 1250 625 313 208 156 16:1 313 156 78 52 39 64:17839201310 note: sckx frequencies shown in khz. sdox sdix pic24h serial clock ssx sckx frame sync pulse sdix sdox processor 2 ssx sckx sdox sdix pic24h serial clock ssx sckx frame sync pulse sdix sdox processor 2 ssx sckx primary prescaler * secondary prescaler f cy f sck =
? 2007 microchip technology inc. preliminary ds70289a-page 137 PIC24HJ32GP202/204 and pic24hj16gp304 register 14-1: spixstat: spix status and control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 spien ? spisidl ? ? ? ? ? bit 15 bit 8 u-0 r/c-0 u-0 u-0 u-0 u-0 r-0 r-0 ? spirov ? ? ? ? spitbf spirbf bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 spien: spix enable bit 1 = enables module and configures sckx, sdox, sdix and ssx as serial port pins 0 = disables module bit 14 unimplemented: read as ? 0 ? bit 13 spisidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 spirov: receive overflow flag bit 1 = a new byte/word is completely received and discarded. the user software has not read the previous data in the spixbuf register. 0 = no overflow has occurred. bit 5-2 unimplemented: read as ? 0 ? bit 1 spitbf: spix transmit buffer full status bit 1 = transmit not yet started, spixtxb is full 0 = transmit started, spixtxb is empty automatically set in hardware when cpu writes spixbuf location, loading spixtxb automatically cleared in hardware when spix module transfers data from spixtxb to spixsr bit 0 spirbf: spix receive buffer full status bit 1 = receive complete, spixrxb is full 0 = receive is not complete, spixrxb is empty automatically set in hardware when spix transfers data from spixsr to spixrxb automatically cleared in hardware when core reads spixbuf location, reading spixrxb
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 138 preliminary ? 2007 microchip technology inc. register 14-2: spi x con1: spix control register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dissck dissdo mode16 smp cke (1) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen ckp msten spre<2:0> ppre<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 dissck: disable sckx pin bit (spi master modes only) 1 = internal spi clock is disabled, pin functions as i/o 0 = internal spi clock is enabled bit 11 dissdo: disable sdox pin bit 1 = sdox pin is not used by module; pin functions as i/o 0 = sdox pin is controlled by the module bit 10 mode16: word/byte communication select bit 1 = communication is word-wide (16 bits) 0 = communication is byte-wide (8 bits) bit 9 smp: spix data input sample phase bit master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time slave mode: smp must be cleared when spix is used in slave mode. bit 8 cke: spix clock edge select bit (1) 1 = serial output data changes on transition from active clock state to idle clock state (see bit 6) 0 = serial output data changes on transition from idle clock state to active clock state (see bit 6) bit 7 ssen: slave select enable bit (slave mode) 1 = ssx pin used for slave mode 0 = ssx pin not used by module. pin controlled by port function. bit 6 ckp: clock polarity select bit 1 = idle state for clock is a high level; active state is a low level 0 = idle state for clock is a low level; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 = slave mode note 1: the cke bit is not used in the framed spi modes. program this bit to ? 0 ? for the framed spi modes (frmen = 1 ).
? 2007 microchip technology inc. preliminary ds70289a-page 139 PIC24HJ32GP202/204 and pic24hj16gp304 bit 4-2 spre<2:0>: secondary prescale bits (master mode) 111 = secondary prescale 1:1 110 = secondary prescale 2:1 ? ? ? 000 = secondary prescale 8:1 bit 1-0 ppre<1:0>: primary prescale bits (master mode) 11 = primary prescale 1:1 10 = primary prescale 4:1 01 = primary prescale 16:1 00 = primary prescale 64:1 register 14-2: spi x con1: spix control register 1 (continued) note 1: the cke bit is not used in the framed spi modes. program this bit to ? 0 ? for the framed spi modes (frmen = 1 ).
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 140 preliminary ? 2007 microchip technology inc. register 14-3: spixcon2: spix control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 frmen spifsd frmpol ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 ? ? ? ? ? ? frmdly ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 frmen : framed spix support bit 1 = framed spix support enabled (ssx pin used as frame sync pulse input/output) 0 = framed spix support disabled bit 14 spifsd : frame sync pulse direction control bit 1 = frame sync pulse input (slave) 0 = frame sync pulse output (master) bit 13 frmpol : frame sync pulse polarity bit 1 = frame sync pulse is active-high 0 = frame sync pulse is active-low bit 12-2 unimplemented: read as ? 0 ? bit 1 frmdly : frame sync pulse edge select bit 1 = frame sync pulse coincides with first bit clock 0 = frame sync pulse precedes first bit clock bit 0 unimplemented: this bit must not be set to ? 1 ? by the user application.
? 2007 microchip technology inc. preliminary ds70289a-page 141 PIC24HJ32GP202/204 and pic24hj16gp304 15.0 inter-integrated circuit (i 2 c) the inter-integrated circuit (i 2 c) module provides complete hardware support for both slave and multi- master modes of the i 2 c serial communication standard, with a 16-bit interface. the i 2 c module has a 2-pin interface: ? the sclx pin is clock ? the sdax pin is data. the i 2 c module offers the following key features: ?i 2 c interface supporting both master and slave modes of operation. ?i 2 c slave mode supports 7- and 10-bit address. ?i 2 c master mode supports 7- and 10-bit address. ?i 2 c port allows bidirectional transfers between master and slaves. ? serial clock synchronization for i 2 c port can be used as a handshake mechanism to suspend and resume serial transfer (sclrel control). ?i 2 c supports multi-master operation, detects bus collision and arbitrates accordingly. 15.1 operating modes the hardware fully implements all the master and slave functions of the i 2 c standard and fast mode specifications, as well as 7 and 10-bit addressing. the i 2 c module can operate either as a slave or a master on an i 2 c bus. the following types of i 2 c operation are supported: ?i 2 c slave operation with 7-bit address ?i 2 c slave operation with 10-bit address ?i 2 c master operation with 7- or 10-bit address for details about the communication sequence in each of these modes, refer to the ?pic24h family reference manual? . 15.2 i 2 c registers i2cxcon and i2cxstat are control and status registers, respectively. the i2cxcon register is readable and writable. the lower six bits of i2cxstat are read-only. the remaining bits of the i2cstat are read/write. ? i2cxrsr is the shift register used for shifting data. ? i2cxrcv is the receive buffer and the register to which data bytes are written, or from which data bytes are read. ? i2cxtrn is the transmit register to which bytes are written during a transmit operation. ? the i2cxadd register holds the slave address. ? a status bit, add10, indicates 10-bit address mode. ? i2cxbrg acts as the baud rate generator (brg) reload value. in receive operations, i2cxrsr and i2cxrcv together form a double-buffered receiver. when i2cxrsr receives a complete byte, it is transferred to i2cxrcv, and an interrupt pulse is generated. 15.3 i 2 c interrupts the i 2 c module generates two interrupt flags: ? mi2cxif (i 2 c master events interrupt flag) ? si2cxif (i 2 c slave events interrupt flag). a separate interrupt is generated for all i 2 c error condi- tions. 15.4 baud rate generator in i 2 c master mode, the reload value for the baud rate generator (brg) is located in the i2cxbrg register. when the brg is loaded with this value, the brg counts down to zero and stops until another reload has taken place. if clock arbitration is taking place, for example, the brg is reloaded when the sclx pin is sampled high. as per the i 2 c standard, f scl can be 100 khz or 400 khz. however, the user application can specify any baud rate up to 1 mhz. i2cxbrg values of ? 0 ? or ? 1 ? are illegal. equation 15-1: serial clock rate note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . i2cxbrg = f cy f cy f scl 10,000,000 ? 1 ? ( )
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 142 preliminary ? 2007 microchip technology inc. figure 15-1: i 2 c? block diagram ( x = 1) internal data bus sclx sdax shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control t cy /2 start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk i2cxrcv
? 2007 microchip technology inc. preliminary ds70289a-page 143 PIC24HJ32GP202/204 and pic24hj16gp304 15.5 i 2 c module addresses the 10-bit i2cxadd register contains the slave mode addresses. if the a10m bit (i2cxcon<10>) is ? 0 ?, the address is interpreted by the module as a 7-bit address. when an address is received, it is compared to the seven least significant bits of the i2cxadd register. if the a10m bit is ? 1 ?, the address is assumed to be a 10-bit address. when an address is received, it is com- pared with the binary value, ? 11110 a9 a8 ? (where a9 and a8 are two most significant bits of i2cxadd). if that value matches, the next address will be compared with the least significant 8 bits of i2cxadd, as speci- fied in the 10-bit addressing protocol. table 15-1: 7-bit i 2 c? slave addresses supported by PIC24HJ32GP202/204 and pic24hj16gp304 15.6 slave address masking the i2cxmsk register (register 15-3) designates address bit positions as ?don?t care? for both 7-bit and 10-bit address modes. setting a particular bit location (= 1 ) in the i2cxmsk register causes the slave module to respond, whether the corresponding address bit value is a ? 0 ? or ? 1 ?. for example, when i2cxmsk is set to ? 00100000 ?, the slave module will detect both addresses, ? 0000000 ? and ? 00100000 ?. to enable address masking, the ipmi (intelligent peripheral management interface) must be disabled by clearing the ipmien bit (i2cxcon<11>). 15.7 ipmi support the control bit ipmien enables the module to support the intelligent peripheral management interface (ipmi). when this bit is set, the module accepts and acts upon all addresses. 15.8 general call address support the general call address can address all devices. when this address is used, all devices should, in theory, respond with an acknowledgement. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r_w = 0 . the general call address is recognized when the general call enable (gcen) bit is set (i2cxcon<7> = 1 ). when the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the i2cxrcv to determine if the address was device-specific or a general call address. 15.9 automatic clock stretch in slave modes, the module can synchronize buffer reads and write to the master device by clock stretching. 15.9.1 transmit clock stretching both 10-bit and 7-bit transmit modes implement clock stretching by asserting the sclrel bit after the falling edge of the ninth clock, if the tbf bit is cleared, indicating the buffer is empty. in slave transmit modes, clock stretching is always performed, irrespective of the stren bit. the user?s isr must set the sclrel bit before transmission is allowed to continue. by holding the sclx line low, the user application has time to service the isr and load the contents of the i2cxtrn before the master device can initiate another transmit sequence. 15.9.2 receive clock stretching the stren bit in the i2cxcon register can be used to enable clock stretching in slave receive mode. when the stren bit is set, the sclx pin will be held low at the end of each data receive sequence. the user?s isr must set the sclrel bit before recep- tion is allowed to continue. by holding the sclx line low, the user application has time to service the isr and read the contents of the i2cxrcv before the mas- ter device can initiate another receive sequence. this prevents buffer overruns. 15.10 software controlled clock stretching (stren = 1 ) when the stren bit is ? 1 ?, the software can clear the sclrel bit to allow software to control the clock stretching. if the stren bit is ? 0 ?, a software write to the sclrel bit is disregarded and has no effect on the sclrel bit. 0x00 general call address or start byte 0x01-0x03 reserved 0x04-0x07 hs mode master codes 0x08-0x77 valid 7-bit addresses 0x78-0x7b valid 10-bit addresses (lower 7 bits) 0x7c-0x7f reserved
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 144 preliminary ? 2007 microchip technology inc. 15.11 slope control the i 2 c standard requires slope control on the sdax and sclx signals for fast mode (400 khz). the control bit, disslw, enables the user application to disable slew rate control if desired. it is necessary to disable the slew rate control for 1 mhz mode. 15.12 clock arbitration clock arbitration occurs when the master deasserts the sclx pin (sclx allowed to float high) during any receive, transmit or restart/stop condition. when the sclx pin is allowed to float high, the baud rate gen- erator (brg) is suspended from counting until the sclx pin is actually sampled high. when the sclx pin is sampled high, the brg is reloaded with the contents of i2cxbrg and begins counting. this process ensures that the sclx high time will always be at least one brg rollover count in the event that the clock is held low by an external device. 15.13 multi-master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitration. when the master outputs address/data bits onto the sdax pin, arbitration takes place when the master outputs a ? 1 ? on sdax by letting sdax float high while another master asserts a ? 0 ?. when the sclx pin floats high, data should be stable. if the expected data on sdax is a ? 1 ? and the data sampled on the sdax pin = 0 , then a bus collision has taken place. the master will set the i 2 c master events interrupt flag and reset the master portion of the i 2 c port to its idle state. 15.14 peripheral pin select limitations the i 2 c module has limited peripheral pin select func- tionality. when the acti2c bit in the fpor configura- tion register is set to ? 1 ?, the module uses the sdax/ sclx pins. if the alti2c bit is ? 0 ? , the module uses the asdax/asclx pins.
? 2007 microchip technology inc. preliminary ds70289a-page 145 PIC24HJ32GP202/204 and pic24hj16gp304 register 15-1: i2cxcon: i2cx control register r/w-0 u-0 r/w-0 r/w-1 hc r/w-0 r/w-0 r/w-0 r/w-0 i2cen ? i2csidl sclrel ipmien a10m disslw smen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 hc r/w-0 hc r/w-0 hc r/w-0 hc r/w-0 hc gcen stren ackdt acken rcen pen rsen sen bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hs = set in hardware hc = cleared in hardware -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 i2cen: i2cx enable bit 1 = enables the i2cx module and configures the sdax and sclx pins as serial port pins 0 = disables the i2cx module. all i 2 c pins are controlled by port functions. bit 14 unimplemented: read as ? 0 ? bit 13 i2csidl: stop in idle mode bit 1 = discontinue module operation when device enters an idle mode 0 = continue module operation in idle mode bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = release sclx clock 0 = hold sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software can write ? 0 ? to initiate stretch and write ? 1 ? to release clock). hardware clear at beginning of slave transmission. hardware clear at end of slave reception. if stren = 0 : bit is r/s (i.e., software can only write ? 1 ? to release clock). hardware clear at beginning of slave transmission. bit 11 ipmien: intelligent peripheral management interface (ipmi) enable bit 1 = ipmi mode is enabled; all addresses acknowledged 0 = ipmi mode disabled bit 10 a10m: 10-bit slave address bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control disabled 0 = slew rate control enabled bit 8 smen: smbus input levels bit 1 = enable i/o pin thresholds compliant with smbus specification 0 = disable smbus input thresholds bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enable interrupt when a general call address is received in the i2cxrsr (module is enabled for reception) 0 = general call address disabled bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with sclrel bit. 1 = enable software or receive clock stretching 0 = disable software or receive clock stretching
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 146 preliminary ? 2007 microchip technology inc. bit 5 ackdt: acknowledge data bit (when operating as i 2 c master, applicable during master receive) value that will be transmitted when the software initiates an acknowledge sequence. 1 = send nack during acknowledge 0 = send ack during acknowledge bit 4 acken: acknowledge sequence enable bit (when operating as i 2 c master, applicable during master receive) 1 = initiate acknowledge sequence on sdax and sclx pins and transmit ackdt data bit. hardware clear at end of master acknowledge sequence. 0 = acknowledge sequence not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c. hardware clear at end of eighth bit of master receive data byte. 0 = receive sequence not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiate stop condition on sdax and sclx pins. hardware clear at end of master stop sequence. 0 = stop condition not in progress bit 1 rsen: repeated start condition enable bit (when operating as i 2 c master) 1 = initiate repeated start condition on sdax and sclx pins. hardware clear at end of master repeated start sequence. 0 = repeated start condition not in progress bit 0 sen: start condition enable bit (when operating as i 2 c master) 1 = initiate start condition on sdax and sclx pins. hardware clear at end of master start sequence. 0 = start condition not in progress register 15-1: i2cxcon: i2cx control register (continued)
? 2007 microchip technology inc. preliminary ds70289a-page 147 PIC24HJ32GP202/204 and pic24hj16gp304 register 15-2: i2cxstat: i2cx status register r-0 hsc r-0 hsc u-0 u-0 u-0 r/c-0 hs r-0 hsc r-0 hsc ackstat trstat ? ? ? bcl gcstat add10 bit 15 bit 8 r/c-0 hs r/c-0 hs r-0 hsc r/c-0 hsc r/c-0 hsc r-0 hsc r-0 hsc r-0 hsc iwcol i2cov d_a p s r_w rbf tbf bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hs = set in hardware hsc = hardware set/cleared -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ackstat: acknowledge status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = nack received from slave 0 = ack received from slave hardware set or clear at end of slave acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware set at beginning of master transmission. hardware clear at end of slave acknowledge. bit 13-11 unimplemented: read as ? 0 ? bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detected during a master operation 0 = no collision hardware set at detection of bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware set when address matches general call address. hardware clear at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware set at match of 2nd byte of matched 10-bit address. hardware clear at stop detection. bit 7 iwcol: write collision detect bit 1 = an attempt to write the i2cxtrn register failed because the i 2 c module is busy 0 = no collision hardware set at occurrence of write to i2cxtrn while busy (cleared by software). bit 6 i2cov: receive overflow flag bit 1 = a byte was received while the i2cxrcv register is still holding the previous byte 0 = no overflow hardware set at attempt to transfer i2 cxrsr to i2cxrcv (cleared by software). bit 5 d_a: data/address bit (when operating as i 2 c slave) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was device address hardware clear at device address match. hardware set by reception of slave byte. bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware set or clear when start, repeated start or stop detected.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 148 preliminary ? 2007 microchip technology inc. bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware set or clear when start, repeated start or stop detected. bit 2 r_w: read/write information bit (when operating as i 2 c slave) 1 = read ? indicates data transfer is output from slave 0 = write ? indicates data transfer is input to slave hardware set or clear after reception of i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive complete, i2cxrcv is full 0 = receive not complete, i2cxrcv is empty hardware set when i2cxrcv is written with received byte. hardware clear when software reads i2cxrcv. bit 0 tbf: transmit buffer full status bit 1 = transmit in progress, i2cxtrn is full 0 = transmit complete, i2cxtrn is empty hardware set when software writes i2cxtrn. hardware clear at completion of data transmission. register 15-2: i2cxstat: i2cx status register (continued)
? 2007 microchip technology inc. preliminary ds70289a-page 149 PIC24HJ32GP202/204 and pic24hj16gp304 register 15-3: i2cxmsk: i2cx sl ave mode address mask register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? amsk9 amsk8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 amsk7 amsk6 amsk5 amsk4 amsk3 amsk2 amsk1 amsk0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as ? 0 ? bit 9-0 amskx: mask for address bit x select bit 1 = enable masking for bit x of incoming message address; bit match not required in this position 0 = disable masking for bit x; bit match required in this position
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 150 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70289a-page 151 PIC24HJ32GP202/204 and pic24hj16gp304 16.0 universal asynchronous receiver transmitter (uart) the universal asynchronous receiver transmitter (uart) module is one of the serial i/o modules avail- able in the PIC24HJ32GP202/204 and pic24hj16gp304 device family. the uart is a full- duplex asynchronous system that can communicate with peripheral devices, such as personal computers, lin, rs-232 and rs-485 interfaces. the module also supports a hardware flow control option with the uxcts and uxrts pins and also includes an irda ? encoder and decoder. the primary features of the uart module are: ? full-duplex 8- or 9-bit data transmission through the uxtx and uxrx pins ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? hardware flow control option with uxcts and uxrts pins ? fully integrated baud rate generator with 16-bit prescaler ? baud rates ranging from 1 mbps to 15 mbps at 16 mips ? 4-deep first-in-first-out (fifo) transmit data buffer ? 4-deep fifo receive data buffer ? parity, framing and buffer overrun error detection ? support for 9-bit mode with address detect (9th bit = 1 ) ? transmit and receive interrupts ? a separate interrupt for all uart error conditions ? loopback mode for diagnostic support ? support for sync and break characters ? support for automatic baud rate detection ? irda encoder and decoder logic ? 16x baud clock output for irda support a simplified block diagram of the uart module is shown in figure 16-1. the uart module consists of the following key hardware elements: ? baud rate generator ? asynchronous transmitter ? asynchronous receiver figure 16-1: uart simplified block diagram note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . uxrx hardware flow control uart receiver uart transmitter uxtx bclk baud rate generator uxrts irda ? uxcts
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 152 preliminary ? 2007 microchip technology inc. 16.1 uart baud rate generator the uart module includes a dedicated 16-bit baud rate generator (brg). the brgx register controls the period of a free-running 16-bit timer. equation 16-1 shows the formula for computation of the baud rate with brgh = 0 . equation 16-1: uart baud rate with brgh = 0 example 16-1 shows the calculation of the baud rate error for the following conditions: ?f cy = 4 mhz ? desired baud rate = 9600 the maximum baud rate (brgh = 0 ) possible is f cy /16 (for brgx = 0 ), and the minimum baud rate possible is f cy /(16 * 65536). equation 16-2 shows the formula for computation of the baud rate with brgh = 1 . equation 16-2: uart baud rate with brgh = 1 the maximum baud rate (brgh = 1 ) possible is f cy /4 (for brgx = 0 ), and the minimum baud rate possible is f cy /(4 * 65536). writing a new value to the brgx register causes the brg timer to be reset (cleared). this ensures the brg does not wait for a timer overflow before generating the new baud rate. example 16-1: baud rate erro r calculation (brgh = 0 ) note: f cy denotes the instruction cycle clock frequency (f osc /2 ). baud rate = f cy 16 ? (brgx + 1) f cy 16 ? baud rate brgx = ? 1 note: f cy denotes the instruction cycle clock frequency (f osc /2). baud rate = f cy 4 ? (brgx + 1) f cy 4 ? baud rate brgx = ? 1 desired baud rate = f cy /(16 (brgx + 1)) solving for brgx value: brgx = ((f cy /desired baud rate)/16) ? 1 brgx = ((4000000/9600)/16) ? 1 brgx = 25 calculated baud rate = 4000000/(16 (25 + 1)) = 9615 error = (calculated baud ra te ? desired baud rate) desired baud rate = (9615 ? 9600)/9600 =0.16%
? 2007 microchip technology inc. preliminary ds70289a-page 153 PIC24HJ32GP202/204 and pic24hj16gp304 16.2 transmitting in 8-bit data mode 1. set up the uart: a) write appropriate values for data, parity and stop bits. b) write appropriate baud rate value to the brgx register. c) set up transmit and receive interrupt enable and priority bits. 2. enable the uart. 3. set the utxen bit (causes a transmit interrupt). write data byte to lower byte of uxtxreg word. the value will be immediately transferred to the transmit shift register (tsr) and the serial bit stream will start shifting out with the next rising edge of the baud clock. alternately, the data byte can be transferred while utxen = 0 , and the user application can set utxen. this causes the serial bit stream to begin immediately, because the baud clock starts from a cleared state. 4. a transmit interrupt will be generated as per interrupt control bits, utxisel<1:0>. 16.3 transmitting in 9-bit data mode 1. set up the uart (as described in section 16.2 ?transmitting in 8-bit data mode? ). 2. enable the uart. 3. set the utxen bit (causes a transmit interrupt). 4. write uxtxreg as a 16-bit value only. a word write to uxtxreg triggers the transfer of the 9-bit data to the tsr. the serial bit stream will start shifting out with the first rising edge of the baud clock. a transmit interrupt will be generated as per the setting of control bits, utxisel<1:0>. 16.4 break and sync transmit sequence the following sequence will send a message frame header made up of a break, followed by an auto-baud sync byte. 1. configure the uart for the desired mode. 2. set utxen and utxbrk, which sets up the break character. 3. load the uxtxreg register with a dummy character to initiate transmission (value is ignored). 4. write 0x55 to uxtxreg, which loads the sync character into the transmit fifo. after the break has been sent, the utxbrk bit is reset by hard- ware. the sync character now starts transmit- ting. 16.5 receiving in 8-bit or 9-bit data mode 1. set up the uart (as described in section 16.2 ?transmitting in 8-bit data mode? ). 2. enable the uart. a receive interrupt will be generated when one or more data characters have been received as per interrupt control bits, urxisel<1:0>. 3. read the oerr bit to determine if an overrun error has occurred. the oerr bit must be reset in software. 4. read uxrxreg. the act of reading the uxrxreg character will move the next character to the top of the receive fifo, including a new set of perr and ferr values. 16.6 flow control using uxcts and uxrts pins uartx clear to send (uxcts ) and request to send (uxrts ) are the two hardware controlled active-low pins associated with the uart module. the uen<1:0> bits in the uxmode register configure these pins. these two pins allow the uart to operate in simplex and flow control modes. they are implemented to control the transmission and the reception between the data terminal equipment (dte). 16.7 infrared support the uart module provides two types of infrared uart support: ? irda clock output to support external irda encoder and decoder device (legacy module support) ? full implementation of the irda encoder and decoder. 16.7.1 external irda support ? irda clock output to support external irda encoder and decoder devices, the bclk pin can be configured to generate the 16x baud clock. with uen<1:0> = 11 , the bclk pin will output the 16x baud clock if the uart module is enabled. the pin can be used to support the irda codec chip. 16.7.2 built-in irda encoder and decoder the uart module includes full implementation of the irda encoder and decoder. the built-in irda encoder and decoder functionality is enabled using the iren bit (uxmode<12>). when iren = 1 is enabled, the receive pin (uxrx) acts as the input from the infrared receiver. the transmit pin (uxtx) acts as the output to the infrared transmitter.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 154 preliminary ? 2007 microchip technology inc. register 16-1: uxmode: uart x mode register r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 uarten ? usidl iren (1) rtsmd ?uen<1:0> bit 15 bit 8 r/w-0 hc r/w-0 r/w-0 hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud urxinv brgh pdsel<1:0> stsel bit 7 bit 0 legend: hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 uarten: uartx enable bit 1 = uartx is enabled; all uartx pins are controlled by uartx as defined by uen<1:0> 0 = uartx is disabled; all uartx pins are controlled by port latches; uartx power consumption minimal bit 14 unimplemented: read as ? 0 ? bit 13 usidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 iren: irda encoder and decoder enable bit (1) 1 = irda encoder and decoder enabled 0 = irda encoder and decoder disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 =uxrts pin in simplex mode 0 =uxrts pin in flow control mode bit 10 unimplemented: read as ? 0 ? bit 9-8 uen<1:0>: uartx enable bits 11 = uxtx, uxrx and bclk pins are enabled and used; uxcts pin controlled by port latches 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin controlled by port latches 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /bclk pins controlled by port latches bit 7 wake: wake-up on start bit detect during sleep mode enable bit 1 = uartx will continue to sample the uxrx pin; interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = no wake-up enabled bit 6 lpback: uartx loopback mode select bit 1 = enable loopback mode 0 = loopback mode is disabled bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next character ? requires reception of a sync field (55h) before other data; cleared in hardware upon completion 0 = baud rate measurement disabled or completed bit 4 urxinv: receive polarity inversion bit 1 = uxrx idle state is ? 0 ? 0 = uxrx idle state is ? 1 ? note 1: this feature is only available for the 16x brg mode (brgh = 0 ).
? 2007 microchip technology inc. preliminary ds70289a-page 155 PIC24HJ32GP202/204 and pic24hj16gp304 bit 3 brgh: high baud rate enable bit 1 = brg generates 4 clocks per bit period (4x baud clock, high-speed mode) 0 = brg generates 16 clocks per bit period (16x baud clock, standard mode) bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop bit selection bit 1 = two stop bits 0 = one stop bit register 16-1: uxmode: uart x mode register (continued) note 1: this feature is only available for the 16x brg mode (brgh = 0 ).
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 156 preliminary ? 2007 microchip technology inc. register 16-2: u x sta: uart x status and control register r/w-0 r/w-0 r/w-0 u-0 r/w-0 hc r/w-0 r-0 r-1 utxisel1 utxinv (1) utxisel0 ? utxbrk utxen utxbf trmt bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 r/c-0 r-0 urxisel<1:0> adden ridle perr ferr oerr urxda bit 7 bit 0 legend: hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15,13 utxisel<1:0>: transmission interrupt mode selection bits 11 = reserved; do not use 10 = interrupt when a character is transferred to the transmit shift register, and as a result, the transmit buffer becomes empty 01 = interrupt when the last character is shifted out of the transmit shift register; all transmit operations are completed 00 = interrupt when a character is transferred to the transmit shift register (this implies there is at least one character open in the transmit buffer) bit 14 utxinv: irda encoder transmit polarity inversion bit (1) 1 = irda encoded, uxtx idle state is ? 1 ? 0 = irda encoded, uxtx idle state is ? 0 ? bit 12 unimplemented: read as ? 0 ? bit 11 utxbrk: transmit break bit 1 = send sync break on next transmission ? start bit, followed by twelve ? 0 ? bits, followed by stop bit; cleared by hardware upon completion 0 = sync break transmission disabled or completed bit 10 utxen: transmit enable bit 1 = transmit enabled, uxtx pin controlled by uartx 0 = transmit disabled, any pending transmission is aborted and buffer is reset. uxtx pin controlled by port. bit 9 utxbf: transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at least one more character can be written bit 8 trmt: transmit shift register empty bit (read-only) 1 = transmit shift register is empty and transmit buf fer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmission is in progress or queued bit 7-6 urxisel<1:0>: receive interrupt mode selection bits 11 = interrupt is set on uxrsr transfer making the receive buffer full (i.e., has 4 data characters) 10 = interrupt is set on uxrsr transfer making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = interrupt is set when any character is received and transferred from the uxrsr to the receive buffer. receive buffer has one or more characters. bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode enabled. if 9-bit mode is not selected, this does not take effect. 0 = address detect mode disabled note 1: value of bit only affects the transmit properties of the module when the irda encoder is enabled (iren = 1 ).
? 2007 microchip technology inc. preliminary ds70289a-page 157 PIC24HJ32GP202/204 and pic24hj16gp304 bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = receiver is active bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current character (character at the top of the receive fifo) 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character (character at the top of the receive fifo) 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit (read/clear only) 1 = receive buffer has overflowed 0 = receive buffer has not overflowed. clearing a previously set oerr bit ( 1 0 transition) will reset the receiver buffer and the uxrsr to the empty state. bit 0 urxda: receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 16-2: u x sta: uart x status and control register (continued) note 1: value of bit only affects the transmit properties of the module when the irda encoder is enabled (iren = 1 ).
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 158 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70289a-page 159 PIC24HJ32GP202/204 and pic24hj16gp304 17.0 10-bit/12-bit analog-to- digital converter (adc) the PIC24HJ32GP202/204 and pic24hj16gp304 devices have up to 13 analog-to-digital conversion (adc) module input channels. the ad12b bit (ad1con1<10>) allows each of the adc modules to be configured as either a 10-bit, 4- sample-and-hold adc (default configuration), or a 12-bit, 1-sample-and-hold adc. 17.1 key features the 10-bit adc configuration has the following key features: ? successive approximation (sar) conversion ? conversion speeds of up to 1.1 msps ? up to 13 analog input pins ? external voltage reference input pins ? simultaneous sampling of up to four analog input pins ? automatic channel scan mode ? selectable conversion trigger source ? selectable buffer fill modes ? operation during cpu sleep and idle modes ? 16-word conversion result buffer the 12-bit adc configuration supports all the above features, except: ? in the 12-bit configuration, conversion speeds of up to 500 ksps are supported ? there is only 1 sample-and-hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported. depending on the particular device pinout, the adc can have up to 13 analog input pins, designated an0 through an12. in addition, there are two analog input pins for external voltage reference connections. these voltage reference inputs can be shared with other ana- log input pins. the actual number of analog input pins and external voltage reference input configuration will depend on the specific device. refer to the device data sheet for fur- ther details. a block diagram of adc for pic24hj16gp304 and pic24hj32gp204 devices is shown in figure 17-1. a block diagram of the adc for the PIC24HJ32GP202 device is shown in figure 17-2. 17.2 adc initialization to configure the adc module: 1. select port pins as analog inputs (ad1pcfgh<15:0> or ad1pcfgl<15:0>). 2. select voltage reference source to match expected range on analog inputs (ad1con2<15:13>). 3. select the analog conversion clock to match desired data rate with processor clock (ad1con3<7:0>). 4. determine how many sample-and-hold chan- nels will be used (ad1con2<9:8> and ad1pcfgh<15:0> or ad1pcfgl<15:0>). 5. select the appropriate sample/conversion sequence (ad1con1<7:5> and ad1con3<12:8>). 6. select the way conversion results are presented in the buffer (ad1con1<9:8>). 7. turn on the adc module (ad1con1<15>). 8. configure adc interrupt (if required): a) clear the ad1if bit. b) select adc interrupt priority. note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . note: the adc module must be disabled before the ad12b bit can be modified.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 160 preliminary ? 2007 microchip technology inc. figure 17-1: adc1 modul e block diagram for pic24hfj16gp304 and pic24hj32gp204 devices s/h + - conversion conversion logic v ref + (1) av ss av dd adc1 data format 16-bit adc output bus interface 00000 00101 00111 01001 00001 00010 00011 00100 00110 01000 01010 01011 an8 an9 an10 an11 an2 an4 an7 an0 an3 an1 an5 ch1 (2) ch2 (2) ch3 (2) ch0 an5 an2 an11 an8 v ref - an4 an1 an10 an7 v ref - an3 an0 an9 an6 v ref - an1 v ref - v ref - (1) sample/sequence control sample ch1,ch2, ch3,ch0 input mux control input switches s/h + - s/h + - s/h + - an6 buffer result note 1: v ref +, v ref - inputs may be multiplexed with other analog inputs. 2: channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. 01100 an12
? 2007 microchip technology inc. preliminary ds70289a-page 161 PIC24HJ32GP202/204 and pic24hj16gp304 figure 17-2: adc1 module block diagram for PIC24HJ32GP202 devices s/h + - conversion conversion logic v ref + (1) av ss av dd adc1 data format 16-bit adc output bus interface 00000 00101 00001 00010 00011 00100 01001 01010 01011 an10 an11 an2 an4 an0 an3 an1 an5 ch1 (2) ch2 (2) ch3 (2) ch0 an5 an2 an11 v ref - an4 an1 an10 v ref - an3 an0 an9 v ref - an1 v ref - v ref - (1) sample/sequence control sample ch1,ch2, ch3,ch0 input mux control input switches s/h + - s/h + - s/h + - buffer result note 1: v ref +, v ref - inputs may be multiplexed with other analog inputs. 2: channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. 01100 an12 an9
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 162 preliminary ? 2007 microchip technology inc. equation 17-1: adc conversion clock period figure 17-3: adc transfer function (10-bit example) figure 17-4: adc conversion clock period block diagram t ad = t cy (adcs + 1) adcs = t ad t cy ? 1 10 0000 0010 (= 514) 10 0000 0011 (= 515) 01 1111 1101 (= 509) 01 1111 1110 (= 510) 01 1111 1111 (= 511) 11 1111 1110 (= 1022) 11 1111 1111 (= 1023) 00 0000 0000 (= 0) 00 0000 0001 (= 1) output code 10 0000 0000 (= 512) (v inh ? v inl ) v refl v refh ? v refl 1024 v refh v refl + 10 0000 0001 (= 513) 512 * (v refh ? v refl ) 1024 v refl + 1023 * (v refh ? v refl ) 1024 v refl + 0 1 adc internal rc clock t osc (1) x 2 adc conversion clock multiplier 1, 2, 3, 4, 5,..., 64 ad1con3<15> t cy t ad 6 ad1con3<5:0> note: refer to figure 7-2 for the derivation of f osc when the pll is enabled. if the pll is not used, f osc is equal to the clock frequency. t osc = 1/ f osc .
? 2007 microchip technology inc. preliminary ds70289a-page 163 PIC24HJ32GP202/204 and pic24hj16gp304 register 17-1: ad1con1: adc1 control register 1 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 adon ?adsidl ? ?ad12b form<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 hc,hs r/c-0 hc, hs ssrc<2:0> ? simsam asam samp done bit 7 bit 0 legend: hc = cleared by hardware hs = set by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adon: adc operating mode bit 1 = adc module is operating 0 =adc is off bit 14 unimplemented: read as ? 0 ? bit 13 adsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 unimplemented: read as ? 0 ? bit 10 ad12b: 10-bit or 12-bit operation mode bit 1 = 12-bit, 1-channel adc operation 0 = 10-bit, 4-channel adc operation bit 9-8 form<1:0>: data output format bits for 10-bit operation: 11 = reserved 10 = reserved 01 = signed integer (d out = ssss sssd dddd dddd , where s = .not.d<9>) 00 = integer (d out = 0000 00dd dddd dddd ) for 12-bit operation: 11 = reserved 10 = reserved 01 = signed integer (d out = ssss sddd dddd dddd , where s = .not.d<11>) 00 = integer (d out = 0000 dddd dddd dddd ) bit 7-5 ssrc<2:0>: sample clock source select bits 111 = internal counter ends sampling and starts conversion (auto-convert) 110 = reserved 101 = reserved 100 = reserved 011 = reserved 010 = gp timer 3 compare ends sampling and starts conversion 001 = active transition on int0 pin ends sampling and starts conversion 000 = clearing sample bit ends sampling and starts conversion bit 4 unimplemented: read as ? 0 ? bit 3 simsam: simultaneous sample select bit (applicable only when chps<1:0> = 01 or 1x ) when ad12b = 1 , simsam is: u-0, unimplemented, read as ? 0 ? 1 = samples ch0, ch1, ch2, ch3 simultaneously (when chps<1:0> = 1x ); or samples ch0 and ch1 simultaneously (when chps<1:0> = 01 ) 0 = samples multiple channels individually in sequence
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 164 preliminary ? 2007 microchip technology inc. bit 2 asam: adc sample auto-start bit 1 = sampling begins immediately after last conversion. samp bit is auto-set. 0 = sampling begins when samp bit is set bit 1 samp: adc sample enable bit 1 = adc sample-and-hold amplifiers are sampling 0 = adc sample-and-hold amplifiers are holding if asam = 0 , software can write ? 1 ? to begin sampling. automatically set by hardware if asam = 1 . if ssrc = 000 , software can write ? 0 ? to end sampling and start conversion. if ssrc 000 , automatically cleared by hardware to end sampling and start conversion. bit 0 done: adc conversion status bit 1 = adc conversion cycle is completed 0 = adc conversion not started or in progress automatically set by hardware when adc conversion is complete. software can write ? 0 ? to clear done status (software not allowed to write ? 1 ?). clearing this bit will not affect any operation in progress. automatically cleared by hardware at start of a new conversion. register 17-1: ad1con1: adc1 control register 1 (continued)
? 2007 microchip technology inc. preliminary ds70289a-page 165 PIC24HJ32GP202/204 and pic24hj16gp304 register 17-2: ad1con2: adc1 control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 vcfg<2:0> ? ? cscna chps<1:0> bit 15 bit 8 r-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufs ? smpi<3:0> bufm alts bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 vcfg<2:0>: converter voltage reference configuration bits bit 12-11 unimplemented: read as ? 0 ? bit 10 cscna: scan input selections for ch0+ during sample a bit 1 = scan inputs 0 = do not scan inputs bit 9-8 chps<1:0>: select channels utilized bits when ad12b = 1 , chps<1:0> is: u-0, unimplemented, read as ? 0 ? 1x =converts ch0, ch1, ch2 and ch3 01 =converts ch0 and ch1 00 =converts ch0 bit 7 bufs: buffer fill status bit (valid only when bufm = 1 ) 1 = adc is currently filling second half of buffer, user application should access data in the first half 0 = adc is currently filling first half of buffer, user application should access data in the second half bit 6 unimplemented: read as ? 0 ? bit 5-2 smpi<3:0>: sample/convert sequences per interrupt selection bits 1111 =interrupts at the completion of conversion for each 16th sample/convert sequence 1110 =interrupts at the completion of conversion for each 15th sample/convert sequence ? ? ? 0001 =interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 =interrupts at the completion of conversion for each sample/convert sequence bit 1 bufm: buffer fill mode select bit 1 = starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt 0 = always starts filling buffer from the beginning bit 0 alts: alternate input sample mode select bit 1 = uses channel input selects for sample a on first sample and sample b on next sample 0 = always uses channel input selects for sample a adref+ adref- 000 a vdd a vss 001 external v ref +a vss 010 a vdd external v ref - 011 external v ref + external v ref - 1xx a vdd avss
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 166 preliminary ? 2007 microchip technology inc. register 17-3: ad1con3: adc1 control register 3 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adrc ? ? samc<4:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adrc: adc conversion clock source bit 1 = adc internal rc clock 0 = clock derived from system clock bit 14-13 unimplemented: read as ? 0 ? bit 12-8 samc<4:0>: auto sample time bits 11111 = 31 t ad ? ? ? 00001 = 1 t ad 00000 = 0 t ad bit 7-0 adcs<7:0>: adc conversion clock select bits 11111111 = t cy (adcs<7:0> + 1) = 256 t cy = t ad ? ? ? 00000010 = t cy (adcs<7:0> + 1) = 3 t cy = t ad 00000001 = t cy (adcs<7:0> + 1) = 2 t cy = t ad 00000000 = t cy (adcs<7:0> + 1) = 1 t cy = t ad
? 2007 microchip technology inc. preliminary ds70289a-page 167 PIC24HJ32GP202/204 and pic24hj16gp304 register 17-4: ad1chs123: adc1 input channel 1, 2, 3 select register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? ch123nb<1:0> ch123sb bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? ch123na<1:0> ch123sa bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-9 ch123nb<1:0>: channel 1, 2, 3 negative input select for sample b bits PIC24HJ32GP202 devices only: if ad12b = 1 : 11 = reserved 10 = reserved 01 = reserved 00 = reserved if ad12b = 0 : 11 = ch1 negative input is an9, ch2 negative input is an10, ch3 negative input is an11 10 = reserved 01 = ch1, ch2, ch3 negative input is v ref - 00 = ch1, ch2, ch3 negative input is v ref - pic24hj32gp204 and pic24hj16gp304 devices only: if ad12b = 1 : 11 = reserved 10 = reserved 01 = reserved 00 = reserved if ad12b = 0 : 11 = ch1 negative input is an9, ch2 negative input is an10, ch3 negative input is an11 10 = ch1 negative input is an6, ch2 negative input is an7, ch3 negative input is an8 01 = ch1, ch2, ch3 negative input is v ref - 00 = ch1, ch2, ch3 negative input is v ref - bit 8 ch123sb: channel 1, 2, 3 positive input select for sample b bit if ad12b = 1 : 1 = reserved 0 = reserved if ad12b = 0 : 1 = ch1 positive input is an3, ch2 positive input is an4, ch3 positive input is an5 0 = ch1 positive input is an0, ch2 positive input is an1, ch3 positive input is an2 bit 7-3 unimplemented: read as ? 0 ?
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 168 preliminary ? 2007 microchip technology inc. bit 2-1 ch123na<1:0>: channel 1, 2, 3 negative input select for sample a bits PIC24HJ32GP202 devices only: if ad12b = 1 : 11 = reserved 10 = reserved 01 = reserved 00 = reserved if ad12b = 0 : 11 = ch1 negative input is an9, ch2 negative input is an10, ch3 negative input is an11 10 = reserved 01 = ch1, ch2, ch3 negative input is v ref - 00 = ch1, ch2, ch3 negative input is v ref - pic24hj32gp204 and pic24hj16gp304 devices only: if ad12b = 1 : 11 = reserved 10 = reserved 01 = reserved 00 = reserved if ad12b = 0 : 11 = ch1 negative input is an9, ch2 negative input is an10, ch3 negative input is an11 10 = ch1 negative input is an6, ch2 negative input is an7, ch3 negative input is an8 01 = ch1, ch2, ch3 negative input is v ref - 00 = ch1, ch2, ch3 negative input is v ref - bit 0 ch123sa: channel 1, 2, 3 positive input select for sample a bit if ad12b = 1 : 1 = reserved 0 = reserved if ad12b = 0 : 1 = ch1 positive input is an3, ch2 positive input is an4, ch3 positive input is an5 0 = ch1 positive input is an0, ch2 positive input is an1, ch3 positive input is an2 register 17-4: ad1chs123: adc1 input channel 1, 2, 3 select register (continued)
? 2007 microchip technology inc. preliminary ds70289a-page 169 PIC24HJ32GP202/204 and pic24hj16gp304 register 17-5: ad1chs0: adc1 input channel 0 select register r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0nb ? ? ch0sb<4:0> bit 15 bit 8 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0na ? ? ch0sa<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ch0nb: channel 0 negative input select for sample b bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is v ref - bit 14-13 unimplemented: read as ? 0 ? bit 12-8 ch0sb<4:0>: channel 0 positive input select for sample b bits pic24hj32gp204 and pic24hj16gp304 devices only: 01100 = channel 0 positive input is an12 ? ? ? 00010 = channel 0 positive input is an2 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 PIC24HJ32GP202 devices only: 01100 = channel 0 positive input is an12 ? ? ? 01000 = reserved 00111 = reserved 00110 = reserved ? ? ? 00010 = channel 0 positive input is an2 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 bit 7 ch0na: channel 0 negative input select for sample a bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is v ref - bit 6-5 unimplemented: read as ? 0 ?
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 170 preliminary ? 2007 microchip technology inc. bit 4-0 ch0sa<4:0>: channel 0 positive input select for sample a bits pic24hj32gp204 and pic24hj16gp304 devices only: 01100 = channel 0 positive input is an12 ? ? ? 00010 = channel 0 positive input is an2 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 PIC24HJ32GP202 devices only: 01100 = channel 0 positive input is an12 ? ? ? 01000 = reserved 00111 = reserved 00110 = reserved ? ? ? 00010 = channel 0 positive input is an2 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 register 17-5: ad1chs0: adc1 input channel 0 select register (continued)
? 2007 microchip technology inc. preliminary ds70289a-page 171 PIC24HJ32GP202/204 and pic24hj16gp304 register 17-6: ad1cssl: adc1 input scan select register low (1) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? css12 css11 css10 css9 css8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css7 css6 css5 css4 css3 css2 css1 css0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 css<12:0>: adc input scan selection bits 1 = select anx for input scan 0 = skip anx for input scan note 1: on devices without nine analog inputs, all ad1cssl bits can be selected. however, inputs selected for scan without a corresponding input on device will convert adref-. register 17-7: ad1pcfgl: adc1 po rt configuration register low (1) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? pcfg12 pcfg11 pcfg10 pcfg9 pcfg8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 pcfg<12:0>: adc port configuration control bits 1 = port pin in digital mode, port read input enabled, adc input multiplexer connected to av ss 0 = port pin in analog mode, port read input disabled, adc samples pin voltage note 1: on devices without nine analog inputs, all pcfg bits are r/w. however, pcfg bits are ignored on ports without a corresponding input on device.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 172 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70289a-page 173 PIC24HJ32GP202/204 and pic24hj16gp304 18.0 special features PIC24HJ32GP202/204 and pic24hj16gp304 devices include several features that are intended to maximize application flexibility and reliability, and mini- mize cost through elimination of external components. these are: ? flexible configuration ? watchdog timer (wdt) ? code protection and codeguard? security ? jtag boundary scan interface ? in-circuit serial programming? (icsp?) ? in-circuit emulation 18.1 configuration bits the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?), to select various device configurations. these bits are mapped starting at program memory location 0xf80000. the device configuration register map is shown in table 18-1. the individual configuration bit descriptions for the fbs, fgs, foscsel, fosc, fwdt, fpor and ficd configuration registers are shown in table 18-2. note that address 0xf80000 is beyond the user pro- gram memory space. it belongs to the configuration memory space (0x800000-0xffffff), which can only be accessed using table reads and table writes. the upper byte of all device configuration registers should always be ? 1111 1111 .? this makes them appear to be nop instructions in the remote event that their locations are ever executed by accident. since configuration bits are not implemented in the corresponding locations, writing ? 1 ? to these locations has no effect on device operation. to prevent the inadvertent configuration changes dur- ing code execution, all programmable configuration bits are write-once. after a bit is initially programmed during a power cycle, it cannot be written to again. changing a device configuration requires that power to the device be cycled. table 18-1: device conf iguration register map note: this data sheet summarizes the features of the PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? . address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0xf80000 fbs ? ? ? ? bss<2:0> bwrp 0xf80002 reserved reserved (1) 0xf80004 fgs ? ? ? ? ? gss<1:0> gwrp 0xf80006 foscsel ieso ? ? ?fnosc<2:0> 0xf80008 fosc fcksm<1:0> iol1way ? ?osciofncposcmd<1:0> 0xf8000a fwdt fwdten windis ? wdtpre wdtpost<3:0> 0xf8000c fpor ? ? ?alti2c ?fpwrt<2:0> 0xf8000e reserved reserved (1) 0xf80010 fuid0 user unit id byte 0 0xf80012 fuid1 user unit id byte 1 0xf80014 fuid2 user unit id byte 2 0xf80016 fuid3 user unit id byte 3 note 1: these reserved bits read as ?1? and must be programmed as ?1?.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 174 preliminary ? 2007 microchip technology inc. table 18-2: PIC24HJ32GP202/204 and pi c24hj16gp304 configuration bits description bit field register description bwrp fbs boot segment program flash write protection 1 = boot segment may be written 0 = boot segment is write-protected bss<2:0> fbs PIC24HJ32GP202 and pic24hj32gp204 devices only boot segment program flash code protection size x11 = no boot program flash segment boot space is 768 instruction words (except interrupt vectors) 110 = standard security; boot program flash segment ends at 0x0007fe 010 = high security; boot program flash segment ends at 0x0007fe boot space is 3840 instruction words (except interrupt vectors) 101 = standard security; boot program flash segment, ends at 0x001ffe 001 = high security; boot program flash segment ends at 0x001ffe boot space is 7936 instruction words (except interrupt vectors) 100 = standard security; boot program flash segment ends at 0x003ffe 000 = high security; boot program flash segment ends at 0x003ffe bss<2:0> fbs pic24hj16gp304 devices only boot segment program flash code protection size x11 = no boot program flash segment boot space is 768 instruction words (except interrupt vectors) 110 = standard security; boot program flash segment ends at 0x0007fe 010 = high security; boot program flash segment ends at 0x0007fe boot space is 3840 instruction words (except interrupt vectors) 101 = standard security; boot program flash segment, ends at 0x001ffe 001 = high security; boot program flash segment ends at 0x001ffe boot space is 5376 instruction words (except interrupt vectors) 100 = standard security; boot program flash segment ends at 0x002bfe 000 = high security; boot program flash segment ends at 0x002bfe gss<1:0> fgs general segment code-protect bit 11 = user program memory is not code-protected 10 = standard security 0x = high security gwrp fgs general segment write-protect bit 1 = user program memory is not write-protected 0 = user program memory is write-protected ieso foscsel two-speed oscillator start-up enable bit 1 = start-up device with frc, then automatically switch to the user-selected oscillator source when ready 0 = start-up device with user-selected oscillator source fnosc<2:0> foscsel initial oscillator source selection bits 111 = internal fast rc (frc) oscillator with postscaler 110 = internal fast rc (frc) oscillator with divide-by-16 101 = lprc oscillator 100 = secondary (lp) oscillator 011 = primary (xt, hs, ec) oscillator with pll 010 = primary (xt, hs, ec) oscillator 001 = internal fast rc (frc) oscillator with pll 000 = frc oscillator
? 2007 microchip technology inc. preliminary ds70289a-page 175 PIC24HJ32GP202/204 and pic24hj16gp304 fcksm<1:0> fosc clock switching mode bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled iol1way fosc peripheral pin select configuration 1 = allow only one re-configuration 0 = allow multiple re-configurations osciofnc fosc osc2 pin function bit (except in xt and hs modes) 1 = osc2 is clock output 0 = osc2 is general purpose digital i/o pin poscmd<1:0> fosc primary oscillator mode select bits 11 = primary oscillator disabled 10 = hs crystal oscillator mode 01 = xt crystal oscillator mode 00 = ec (external clock) mode fwdten fwdt watchdog timer enable bit 1 = watchdog timer always enabled (lprc oscillator cannot be disabled. clearing the swdten bit in the rcon register will have no effect.) 0 = watchdog timer enabled/disabled by user software (lprc can be disabled by clearing the swdten bit in the rcon register) windis fwdt watchdog timer window enable bit 1 = watchdog timer in non-window mode 0 = watchdog timer in window mode wdtpre fwdt watchdog timer prescaler bit 1 = 1:128 0 = 1:32 wdtpost<3:0> fwdt watchdog timer postscaler bits 1111 = 1:32,768 1110 = 1:16,384 . . . 0001 = 1:2 0000 = 1:1 alti2c fpor alternate i 2 c pins 1 = i 2 c mapped to sda1/scl1 pins 0 = i 2 c mapped to asda1/ascl1 pins fpwrt<2:0> fpor power-on reset timer value select bits 111 = pwrt = 128 ms 110 = pwrt = 64 ms 101 = pwrt = 32 ms 100 = pwrt = 16 ms 011 = pwrt = 8 ms 010 = pwrt = 4 ms 001 = pwrt = 2 ms 000 = pwrt = disabled table 18-2: PIC24HJ32GP202/204 and pic24h j16gp304 config uration bits description (continued) bit field register description
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 176 preliminary ? 2007 microchip technology inc. 18.2 on-chip voltage regulator all of the PIC24HJ32GP202/204 and pic24hj16gp304 devices power their core digital logic at a nominal 2.5v. this can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3v. to simplify system design, all devices in the PIC24HJ32GP202/204 and pic24hj16gp304 family incorporate an on-chip regu- lator that allows the device to run its core logic from v dd . the regulator provides power to the core from the other v dd pins. when the regulator is enabled, a low-esr (less than 5 ohms) capacitor (such as tantalum or ceramic) must be connected to the v ddcore /v cap pin (figure 18-1). this helps to maintain the stability of the regulator. the recommended value for the filter capac- itor is provided in section table 21-13: ?internal voltage regulator specifications? located in section 21.1 ?dc characteristics? . on a por , it takes approximately 20 s for the on-chip voltage regulator to generate an output voltage. during this time, designated as t startup , code execution is disabled. t startup is applied every time the device resumes operation after any power-down. figure 18-1: conne ctions for the on-chip voltage regulator (1) 18.3 bor: brown-out reset the brown-out reset (bor) module is based on an internal voltage reference circuit that monitors the reg- ulated voltage v ddcore . the main purpose of the bor module is to generate a device reset when a brown- out condition occurs. brown-out conditions are gener- ally caused by glitches on the ac mains (for example, missing portions of the ac cycle waveform due to bad power transmission lines, or voltage sags due to exces- sive current draw when a large inductive load is turned on). a bor generates a reset pulse, which resets the device. the bor selects the clock source, based on the device configuration bit values (fnosc<2:0> and poscmd<1:0>). if an oscillator mode is selected, the bor activates the oscillator start-up timer (ost). the system clock is held until ost expires. if the pll is used, the clock is held until the lock bit (osccon<5>) is ? 1 ?. concurrently, the pwrt time-out (tpwrt) will be applied before the internal reset is released. if tpwrt = 0 and a crystal oscillator is being used, a nominal delay of tfscm = 100 is applied. the total delay in this case is tfscm. the bor status bit (rcon<1>) is set to indicate that a bor has occurred. if the bor circuit is enabled, it continues to operate while in sleep or idle mode and resets the device in case vdd falls below the bor threshold voltage. note 1: these are typical operating voltages. refer to section table 21-13: ?internal volt- age regulator specifications? located in section 21.1 ?dc characteristics? for the full operating ranges of v dd and v ddcore . v dd v ddcore /v cap v ss pic24h c f 3.3v
? 2007 microchip technology inc. preliminary ds70289a-page 177 PIC24HJ32GP202/204 and pic24hj16gp304 18.4 watchdog timer (wdt) for PIC24HJ32GP202/204 and pic24hj16gp304 devices, the wdt is driven by the lprc oscillator. when the wdt is enabled, the clock source is also enabled. 18.4.1 prescaler/postscaler the nominal wdt clock source from lprc is 32 khz. this feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. the prescaler is set by the wdtpre configuration bit. with a 32 khz input, the prescaler yields a nominal wdt time-out period (t wdt ) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. a variable postscaler divides down the wdt prescaler output and allows for a wide range of time-out periods. the postscaler is controlled by the wdtpost<3:0> configuration bits (fwdt<3:0>), which allows the selection of 16 settings, from 1:1 to 1:32,768. using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. the wdt, prescaler and postscaler are reset: ? on any device reset ? on the completion of a clock switch, whether invoked by software (i.e., setting the oswen bit after changing the nosc bits) or by hardware (i.e., fail-safe clock monitor) ? when a pwrsav instruction is executed (sleep or idle mode is entered) ? when the device exits sleep or idle mode to resume normal operation ?by a clrwdt instruction during normal execution 18.4.2 sleep and idle modes if the wdt is enabled, it will continue to run during sleep or idle modes. when the wdt time-out occurs, the device will wake the device and code execution will continue from where the pwrsav instruction was executed. the corresponding sleep or idle bits (rcon<3,2>) will need to be cleared in software after the device wakes up. 18.4.3 enabling wdt the wdt is enabled or disabled by the fwdten configuration bit in the fwdt configuration register. when the fwdten configuration bit is set, the wdt is always enabled. the wdt flag bit, wdto (rcon<4>), is not automatically cleared following a wdt time-out. to detect subsequent wdt events, the flag must be cleared in software. the wdt can be optionally controlled in software when the fwdten configuration bit has been programmed to ? 0 ?. the wdt is enabled in software by setting the swdten control bit (rcon<5>). the swdten control bit is cleared on any device reset. the software wdt option allows the user application to enable the wdt for critical code segments and disable the wdt during non-critical segments for maximum power sav- ings. figure 18-2: wdt block diagram note: the clrwdt and pwrsav instructions clear the prescaler and postscaler counts when executed. note: if the windis bit (fwdt<6>) is cleared, the clrwdt instruction should be executed by the application software only during the last 1/4 of the wdt period. this clrwdt window can be determined by using a timer. if a clrwdt instruction is executed before this window, a wdt reset occurs. all device resets transition to new clock source exit sleep or idle mode pwrsav instruction clrwdt instruction 0 1 wdtpre wdtpost<3:0> watchdog timer prescaler (divide by n1) postscaler (divide by n2) sleep/idle wdt wdt window select windis wdt clrwdt instruction swdten fwdten lprc clock rs rs wake-up reset
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 178 preliminary ? 2007 microchip technology inc. 18.5 jtag interface PIC24HJ32GP202/204 and pic24hj16gp304 devices implement a jtag interface, which supports boundary scan device testing, as well as in-circuit pro- gramming. detailed information on this interface will be provided in future revisions of the document. 18.6 code protection and codeguard? security the PIC24HJ32GP202/204 and pic24hj16gp304 product families offer the intermediate implementation of codeguard security. codeguard security allows multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip. this feature helps to protect individual intellectual property in collaborative system designs. when coupled with software encryption libraries, codeguard security can be used to securely update flash even when multiple ips reside on the single chip. the code protection features are controlled by the configuration registers: fbs and fgs. the secure segment and ram is not implemented. table 18-3: code flash security segment sizes for 32 kbyte devices table 18-4: code flash security segment sizes for 16 kbyte devices note: refer to codeguard security reference manual (ds70180) for further information on usage, configuration and operation of codeguard security. config bits bss<2:0>=x11 0k bss<2:0>=x10 256 bss<2:0>=x01 768 bss<2:0>=x00 1792 0057feh 0001feh 000200h 000000h vs = 256 iw 0007feh 000800h 001ffeh 002000h gs = 3840 iw 003ffeh 004000h 0057feh 0001feh 000200h 000000h vs = 256 iw 0007feh 000800h 001ffeh 002000h 003ffeh 004000h gs = 10249 iw bs = 768 iw 0057feh 0001feh 000200h 000000h vs = 256 iw 0007feh 000800h 001ffeh 002000h 003ffeh 004000h gs = 7168 iw bs = 3840 iw 0057feh 0001feh 000200h 000000h vs = 256 iw 0007feh 000800h 001ffeh 002000h gs = 3072 iw 003ffeh 004000h bs = 7936 iw config bits bss<2:0>=x11 0k bss<2:0>=x10 256 bss<2:0>=x01 768 bss<2:0>=x00 1792 002bfeh 0001feh 000200h 000000h vs = 256 iw 0007feh 000800h 001ffeh 002000h gs = 3840 iw 002bfeh 0001feh 000200h 000000h vs = 256 iw 0007feh 000800h 001ffeh 002000h gs = 4608 iw bs = 768 iw 002bfeh 0001feh 000200h 000000h vs = 256 iw 0007feh 000800h 001ffeh 002000h gs = 1536 iw bs = 3840 iw 002bfeh 0001feh 000200h 000000h vs = 256 iw 0007feh 000800h 001ffeh 002000h bs = 5376 iw
? 2007 microchip technology inc. preliminary ds70289a-page 179 PIC24HJ32GP202/204 and pic24hj16gp304 18.7 in-circuit serial programming PIC24HJ32GP202/204 and pic24hj16gp304 family microcontrollers can be serially programmed while in the end application circuit. this is done with two lines for clock and data, and three other lines for power, ground and the programming sequence. serial pro- gramming allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. serial programming also allows the most recent firmware or a custom firmware to be programmed. refer to the ? dspic30f/33f flash programming specification? (ds70152) document for details about in-circuit serial programming (icsp). any of the following three pairs of programming clock/ data pins can be used: ? pgc1/emuc1 and pgd1/emud1 ? pgc2/emuc2 and pgd2/emud2 ? pgc3/emuc3 and pgd3/emud3 18.8 in-circuit debugger when mplab ? icd 2 is selected as a debugger, the in- circuit debugging functionality is enabled. this function allows simple debugging functions when used with mplab ide. debugging functionality is controlled through the emulation/debug clock (emucx) and emulation/debug data (emudx) pin functions. any of the following three pairs of debugging clock/data pins can be used: ? pgc1/emuc1 and pgd1/emud1 ? pgc2/emuc2 and pgd2/emud2 ? pgc3/emuc3 and pgd3/emud3 to make use of the in-circuit debugger function of the device, the design must implement icsp connections to mclr , v dd , v ss , pgc, pgd and the emudx/ emucx pin pair. in addition, when the feature is enabled, some of the resources are not available for general use. these resources include the first 80 bytes of data ram and two i/o pins.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 180 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70289a-page 181 PIC24HJ32GP202/204 and pic24hj16gp304 19.0 instruction set summary the pic24h instruction set is identical to that of the pic24f, and is a subset of the dspic30f/33f instruction set. most instructions are a single program memory word (24 bits). only three instructions require two program memory locations. each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into five basic categories: ? word or byte-oriented operations ? bit-oriented operations ? literal operations ? dsp operations ? control operations table 19-1 shows the general symbols used in describing the instructions. the pic24h instruction set summary in table 19-2 lists all the instructions, along with the status flags affected by each instruction. most word or byte-oriented w register instructions (including barrel shift instructions) have three operands: ? the first source operand which is typically a register ?wb? without any address modifier ? the second source operand which is typically a register ?ws? with or without an address modifier ? the destination of the result which is typically a register ?wd? with or without an address modifier however, word or byte-oriented file register instruc- tions have two operands: ? the file register specified by the value ?f? ? the destination, which could either be the file register ?f? or the w0 register, which is denoted as ?wreg? most bit-oriented instructions (including simple rotate/shift instructions) have two operands: ? the w register (with or without an address modifier) or file register (specified by the value of ?ws? or ?f?) ? the bit in the w register or file register (specified by a literal value or indirectly by the contents of register ?wb?) the literal instructions that involve data movement may use some of the following operands: ? a literal value to be loaded into a w register or file register (specified by the value of ?k?) ? the w register or file register where the literal value is to be loaded (specified by ?wb? or ?f?) however, literal instructions that involve arithmetic or logical operations use some of the following operands: ? the first source operand which is a register ?wb? without any address modifier ? the second source operand which is a literal value ? the destination of the result (only if not the same as the first source operand) which is typically a register ?wd? with or without an address modifier the control instructions may use some of the following operands: ? a program memory address ? the mode of the table read and table write instructions note: this data sheet summarizes the features of this group of PIC24HJ32GP202/204 and pic24hj16gp304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?pic24h family reference manual? .
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 182 preliminary ? 2007 microchip technology inc. all instructions are single word. ceratian of them were made double word instructions so that all the required information is available in these 48 bits. in the second word, the 8 msbs are ? 0 ?s. if this second word is exe- cuted as an instruction (by itself), it will execute as a nop . most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . notable exceptions are the bra (uncondi- tional/computed branch), indirect call/goto , all table reads and writes and return/retfie instructions, which are single-word instructions but take two or three cycles. certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or double word instruction. moreover, double word moves require two cycles. the double word instructions execute in two instruction cycles. note: for more details on the instruction set, refer to the ?dspic30f/33f programmer?s reference manual? (ds70157). table 19-1: symbols used in opcode descriptions field description #text means literal defined by ? text ? (text) means ?content of text ? [text] means ?the location addressed by text ? { } optional field or operation register bit field .b byte mode selection .d double word mode selection .s shadow register select .w word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...15} c, dc, n, ov, z mcu status bits: carry, digit carry, negative, overflow, sticky zero expr absolute address, label or expression (resolved by the linker) f file register address {0x0000...0x1fff} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for byte mode, {0:1023} for word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; lsb must be ? 0 ? none field does not require an entry, may be blank pc program counter slit10 10-bit signed literal {-512...511} slit16 16-bit signed literal {-32768...32767} slit6 6-bit signed literal {-16...16} wb base w register {w0..w15} wd destination w register { wd, [wd], [wd++], [wd--], [++wd], [--wd] } wdo destination w register { wnd, [wnd], [wnd++], [wnd--], [++wnd], [--wnd], [wnd+wb] } wm,wn dividend, divisor working r egister pair (direct addressing) wm*wm multiplicand and multiplier working r egister pair for square instructions {w4 * w4,w5 * w5,w6 * w6,w7 * w7} wn one of 16 working registers {w0..w15}
? 2007 microchip technology inc. preliminary ds70289a-page 183 PIC24HJ32GP202/204 and pic24hj16gp304 wnd one of 16 destination working registers {w0..w15} wns one of 16 source working registers {w0..w15} wreg w0 (working register used in file register instructions) ws source w register { ws, [ws], [ws++], [ws--], [++ws], [--ws] } wso source w register { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] } table 19-1: symbols used in opcode descriptions (continued) field description
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 184 preliminary ? 2007 microchip technology inc. table 19-2: instruction set overview base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected 1 add add f f = f + wreg 1 1 c,dc,n,ov,z add f,wreg wreg = f + wreg 1 1 c,dc,n,ov,z add #lit10,wn wd = lit10 + wd 1 1 c,dc,n,ov,z add wb,ws,wd wd = wb + ws 1 1 c,dc,n,ov,z add wb,#lit5,wd wd = wb + lit5 1 1 c,dc,n,ov,z 2 addc addc f f = f + wreg + (c) 1 1 c,dc,n,ov,z addc f,wreg wreg = f + wreg + (c) 1 1 c,dc,n,ov,z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c,dc,n,ov,z addc wb,ws,wd wd = wb + ws + (c) 1 1 c,dc,n,ov,z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c,dc,n,ov,z 3 and and f f = f .and. wreg 1 1 n,z and f,wreg wreg = f .and. wreg 1 1 n,z and #lit10,wn wd = lit10 .and. wd 1 1 n,z and wb,ws,wd wd = wb .and. ws 1 1 n,z and wb,#lit5,wd wd = wb .and. lit5 1 1 n,z 4 asr asr f f = arithmetic right shift f 1 1 c,n,ov,z asr f,wreg wreg = arithmetic right shift f 1 1 c,n,ov,z asr ws,wd wd = arithmetic right shift ws 1 1 c,n,ov,z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n,z asr wb,#lit5,wnd wnd = arithmetic right shift wb by lit5 1 1 n,z 5 bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none 6 bra bra c,expr branch if carry 1 1 (2) none bra ge,expr branch if greater than or equal 1 1 (2) none bra geu,expr branch if unsigned greater than or equal 1 1 (2) none bra gt,expr branch if greater than 1 1 (2) none bra gtu,expr branch if unsigned greater than 1 1 (2) none bra le,expr branch if less than or equal 1 1 (2) none bra leu,expr branch if unsigned less than or equal 1 1 (2) none bra lt,expr branch if less than 1 1 (2) none bra ltu,expr branch if unsigned less than 1 1 (2) none bra n,expr branch if negative 1 1 (2) none bra nc,expr branch if not carry 1 1 (2) none bra nn,expr branch if not negative 1 1 (2) none bra nz,expr branch if not zero 1 1 (2) none bra expr branch unconditionally 1 2 none bra z,expr branch if zero 1 1 (2) none bra wn computed branch 1 2 none 7 bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none 8 bsw bsw.c ws,wb write c bit to ws 1 1 none bsw.z ws,wb write z bit to ws 1 1 none 9 btg btg f,#bit4 bit toggle f 1 1 none btg ws,#bit4 bit toggle ws 1 1 none 10 btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none 11 btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none
? 2007 microchip technology inc. preliminary ds70289a-page 185 PIC24HJ32GP202/204 and pic24hj16gp304 12 btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws to c 1 1 c btst.z ws,wb bit test ws to z 1 1 z 13 btsts btsts f,#bit4 bit test then set f 1 1 z btsts.c ws,#bit4 bit test ws to c, then set 1 1 c btsts.z ws,#bit4 bit test ws to z, then set 1 1 z 14 call call lit23 call subroutine 2 2 none call wn call indirect subroutine 1 2 none 15 clr clr f f = 0x0000 1 1 none clr wreg wreg = 0x0000 1 1 none clr ws ws = 0x0000 1 1 none 16 clrwdt clrwdt clear watchdog timer 1 1 wdto,sleep 17 com com f f = f 11 n,z com f,wreg wreg = f 11 n,z com ws,wd wd = ws 11 n,z 18 cp cp f compare f with wreg 1 1 c,dc,n,ov,z cp wb,#lit5 compare wb with lit5 1 1 c,dc,n,ov,z cp wb,ws compare wb with ws (wb ? ws) 1 1 c,dc,n,ov,z 19 cp0 cp0 f compare f with 0x0000 1 1 c,dc,n,ov,z cp0 ws compare ws with 0x0000 1 1 c,dc,n,ov,z 20 cpb cpb f compare f with wreg, with borrow 1 1 c,dc,n,ov,z cpb wb,#lit5 compare wb with lit5, with borrow 1 1 c,dc,n,ov,z cpb wb,ws compare wb with ws, with borrow (wb ? ws ? c ) 1 1 c,dc,n,ov,z 21 cpseq cpseq wb, wn compare wb with wn, skip if = 1 1 (2 or 3) none 22 cpsgt cpsgt wb, wn compare wb with wn, skip if > 1 1 (2 or 3) none 23 cpslt cpslt wb, wn compare wb with wn, skip if < 1 1 (2 or 3) none 24 cpsne cpsne wb, wn compare wb with wn, skip if ? 1 1 (2 or 3) none 25 daw daw wn wn = decimal adjust wn 1 1 c 26 dec dec f f = f ? 1 1 1 c,dc,n,ov,z dec f,wreg wreg = f ? 1 1 1 c,dc,n,ov,z dec ws,wd wd = ws ? 1 1 1 c,dc,n,ov,z 27 dec2 dec2 f f = f ? 2 1 1 c,dc,n,ov,z dec2 f,wreg wreg = f ? 2 1 1 c,dc,n,ov,z dec2 ws,wd wd = ws ? 2 1 1 c,dc,n,ov,z 28 disi disi #lit14 disable interrupts for k instruction cycles 1 1 none 29 div div.s wm,wn signed 16/16-bit integer divide 1 18 n,z,c,ov div.sd wm,wn signed 32/16-bit integer divide 1 18 n,z,c,ov div.u wm,wn unsigned 16/16-bit integer divide 1 18 n,z,c,ov div.ud wm,wn unsigned 32/16-bit integer divide 1 18 n,z,c,ov 30 exch exch wns,wnd swap wns with wnd 1 1 none 31 fbcl fbcl ws,wnd find bit change from left (msb) side 1 1 c 32 ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c 33 ff1r ff1r ws,wnd find first one from right (lsb) side 1 1 c 34 goto goto expr go to address 2 2 none goto wn go to indirect 1 2 none table 19-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 186 preliminary ? 2007 microchip technology inc. 35 inc inc f f = f + 1 1 1 c,dc,n,ov,z inc f,wreg wreg = f + 1 1 1 c,dc,n,ov,z inc ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 36 inc2 inc2 f f = f + 2 1 1 c,dc,n,ov,z inc2 f,wreg wreg = f + 2 1 1 c,dc,n,ov,z inc2 ws,wd wd = ws + 2 1 1 c,dc,n,ov,z 37 ior ior f f = f .ior. wreg 1 1 n,z ior f,wreg wreg = f .ior. wreg 1 1 n,z ior #lit10,wn wd = lit10 .ior. wd 1 1 n,z ior wb,ws,wd wd = wb .ior. ws 1 1 n,z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n,z 38 lnk lnk #lit14 link frame pointer 1 1 none 39 lsr lsr f f = logical right shift f 1 1 c,n,ov,z lsr f,wreg wreg = logical right shift f 1 1 c,n,ov,z lsr ws,wd wd = logical right shift ws 1 1 c,n,ov,z lsr wb,wns,wnd wnd = logical right shift wb by wns 1 1 n,z lsr wb,#lit5,wnd wnd = logical right shift wb by lit5 1 1 n,z 40 mov mov f,wn move f to wn 1 1 none mov f move f to f 1 1 n,z mov f,wreg move f to wreg 1 1 n,z mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 n,z mov.d wns,wd move double from w(ns):w(ns + 1) to wd 1 2 none mov.d ws,wnd move double from ws to w(nd + 1):w(nd) 1 2 none 41 mul mul.ss wb,ws,wnd {wnd + 1, wnd} = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd + 1, wnd} = signed(wb) * unsigned(ws) 1 1 none mul.us wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * signed(ws) 1 1 none mul.uu wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(ws) 11 none mul.su wb,#lit5,wnd {wnd + 1, wnd} = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(lit5) 11 none mul f w3:w2 = f * wreg 1 1 none 42 neg neg f f = f + 1 1 1 c,dc,n,ov,z neg f,wreg wreg = f + 1 1 1 c,dc,n,ov,z neg ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 43 nop nop no operation 1 1 none nopr no operation 1 1 none 44 pop pop f pop f from top-of-stack (tos) 1 1 none pop wdo pop from top-of-stack (tos) to wdo 1 1 none pop.d wnd pop from top-of-stack (tos) to w(nd):w(nd + 1) 12 none pop.s pop shadow registers 1 1 all 45 push push f push f to top-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns + 1) to top-of-stack (tos) 1 2 none push.s push shadow registers 1 1 none 46 pwrsav pwrsav #lit1 go into sleep or idle mode 1 1 wdto,sleep table 19-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected
? 2007 microchip technology inc. preliminary ds70289a-page 187 PIC24HJ32GP202/204 and pic24hj16gp304 47 rcall rcall expr relative call 1 2 none rcall wn computed call 1 2 none 48 repeat repeat #lit14 repeat next instruction lit14 + 1 times 1 1 none repeat wn repeat next instruction (wn) + 1 times 1 1 none 49 reset reset software device reset 1 1 none 50 retfie retfie return from interrupt 1 3 (2) none 51 retlw retlw #lit10,wn return with literal in wn 1 3 (2) none 52 return return return from subroutine 1 3 (2) none 53 rlc rlc f f = rotate left through carry f 1 1 c,n,z rlc f,wreg wreg = rotate left through carry f 1 1 c,n,z rlc ws,wd wd = rotate left through carry ws 1 1 c,n,z 54 rlnc rlnc f f = rotate left (no carry) f 1 1 n,z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n,z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n,z 55 rrc rrc f f = rotate right through carry f 1 1 c,n,z rrc f,wreg wreg = rotate right through carry f 1 1 c,n,z rrc ws,wd wd = rotate right through carry ws 1 1 c,n,z 56 rrnc rrnc f f = rotate right (no carry) f 1 1 n,z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n,z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n,z 57 se se ws,wnd wnd = sign-extended ws 1 1 c,n,z 58 setm setm f f = 0xffff 1 1 none setm wreg wreg = 0xffff 1 1 none setm ws ws = 0xffff 1 1 none 59 sl sl f f = left shift f 1 1 c,n,ov,z sl f,wreg wreg = left shift f 1 1 c,n,ov,z sl ws,wd wd = left shift ws 1 1 c,n,ov,z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n,z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n,z 60 sub sub f f = f ? wreg 1 1 c,dc,n,ov,z sub f,wreg wreg = f ? wreg 1 1 c,dc,n,ov,z sub #lit10,wn wn = wn ? lit10 1 1 c,dc,n,ov,z sub wb,ws,wd wd = wb ? ws 1 1 c,dc,n,ov,z sub wb,#lit5,wd wd = wb ? lit5 1 1 c,dc,n,ov,z 61 subb subb f f = f ? wreg ? (c ) 1 1 c,dc,n,ov,z subb f,wreg wreg = f ? wreg ? (c ) 1 1 c,dc,n,ov,z subb #lit10,wn wn = wn ? lit10 ? (c ) 1 1 c,dc,n,ov,z subb wb,ws,wd wd = wb ? ws ? (c ) 1 1 c,dc,n,ov,z subb wb,#lit5,wd wd = wb ? lit5 ? (c ) 1 1 c,dc,n,ov,z 62 subr subr f f = wreg ? f 1 1 c,dc,n,ov,z subr f,wreg wreg = wreg ? f 1 1 c,dc,n,ov,z subr wb,ws,wd wd = ws ? wb 1 1 c,dc,n,ov,z subr wb,#lit5,wd wd = lit5 ? wb 1 1 c,dc,n,ov,z 63 subbr subbr f f = wreg ? f ? (c ) 1 1 c,dc,n,ov,z subbr f,wreg wreg = wreg ? f ? (c ) 1 1 c,dc,n,ov,z subbr wb,ws,wd wd = ws ? wb ? (c ) 1 1 c,dc,n,ov,z subbr wb,#lit5,wd wd = lit5 ? wb ? (c ) 1 1 c,dc,n,ov,z 64 swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none 65 tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 2 none table 19-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 188 preliminary ? 2007 microchip technology inc. 66 tblrdl tblrdl ws,wd read prog<15:0> to wd 1 2 none 67 tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none 68 tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none 69 ulnk ulnk unlink frame pointer 1 1 none 70 xor xor f f = f .xor. wreg 1 1 n,z xor f,wreg wreg = f .xor. wreg 1 1 n,z xor #lit10,wn wd = lit10 .xor. wd 1 1 n,z xor wb,ws,wd wd = wb .xor. ws 1 1 n,z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n,z 71 ze ze ws,wnd wnd = zero-extend ws 1 1 c,z,n table 19-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected
? 2007 microchip technology inc. preliminary ds70289a-page 189 PIC24HJ32GP202/204 and pic24hj16gp304 20.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c18 and mplab c30 c compilers -mplink tm object linker/ mplib tm object librarian - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab real ice? in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers - picstart ? plus development programmer - mplab pm3 device programmer - pickit? 2 development programmer ? low-cost demonstration and development boards and evaluation kits 20.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? visual device initializer for easy register initialization ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as hi-tech software c compilers and iar c compilers the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 190 preliminary ? 2007 microchip technology inc. 20.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all pic mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 20.3 mplab c18 and mplab c30 c compilers the mplab c18 and mplab c30 code development systems are complete ansi c compilers for microchip?s pic18 and pic24 families of microcontrol- lers and the dspic30 and dspic33 family of digital sig- nal controllers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 20.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 20.5 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 20.6 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c18 and mplab c30 c compilers, and the mpasm and mplab asm30 assemblers. the software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
? 2007 microchip technology inc. preliminary ds70289a-page 191 PIC24HJ32GP202/204 and pic24hj16gp304 20.7 mplab ice 2000 high-performance in-circuit emulator the mplab ice 2000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. the architecture of the mplab ice 2000 in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows ? 32-bit operating system were chosen to best make these features available in a simple, unified application. 20.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the mplab real ice probe is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with the popular mplab icd 2 system (rj11) or with the new high-speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). mplab real ice is field upgradeable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 20.9 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash pic mcus and can be used to develop for these and other pic mcus and dspic dscs. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost- effective, in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single step- ping and watching variables, and cpu status and peripheral registers. running at full speed enables testing hardware and applications in real time. mplab icd 2 also serves as a development programmer for selected pic devices. 20.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an sd/mmc card for file storage and secure data applications.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 192 preliminary ? 2007 microchip technology inc. 20.11 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most pic devices in dip packages up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 20.12 pickit 2 development programmer the pickit? 2 development programmer is a low-cost programmer and selected flash device debugger with an easy-to-use interface for programming many of microchip?s baseline, mid-range and pic18f families of flash memory microcontrollers. the pickit 2 starter kit includes a prototyping development board, twelve sequential lessons, software and hi-tech?s picc? lite c compiler, and is designed to help get up to speed quickly using pic ? microcontrollers. the kit provides everything needed to program, evaluate and develop applications using microchip?s powerful, mid-range flash memory family of microcontrollers. 20.13 demonstration, development and evaluation boards a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. check the microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
? 2007 microchip technology inc. preliminary ds70289a-page 193 PIC24HJ32GP202/204 and pic24hj16gp304 21.0 electrical characteristics this section provides an overview of PIC24HJ32GP202/204 and pic24hj16gp304 electrical characteristics. additional information will be provided in future revisions of this document as it becomes available. absolute maximum ratings for the PIC24HJ32GP202/204 and pic24hj16gp304 family are listed below. exposure to these maximum rating conditions for extended periods can affect device reliability. functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. absolute maximum ratings (1) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any combined analog and digital pin and mclr , with respect to v ss ......................... -0.3v to (v dd + 0.3v) voltage on any digital-only pin with respect to v ss .................................................................................. -0.3v to +5.6v voltage on v ddcore with respect to v ss ................................................................................................ 2.25v to 2.75v maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin (2) ...........................................................................................................................250 ma maximum output current sunk by any i/o pin (3) ........................................................................................................4 ma maximum output current sourced by any i/o pin (3) ...................................................................................................4 ma maximum current sunk by all ports .............................................................................................. .........................200 ma maximum current sourced by all ports (2) ...............................................................................................................200 ma note 1: stresses above those listed under ?absolute maximum ratings? can cause permanent damage to the device. this is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods can affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see table 21-2). 3: exceptions are clkout, which is able to sink/source 25 ma, and the v ref +, v ref -, sclx, sdax, pgcx and pgdx pins, which are able to sink/source 12 ma.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 194 preliminary ? 2007 microchip technology inc. 21.1 dc characteristics table 21-1: operating mips vs. voltage characteristic v dd range (in volts) temp range (in c) max mips PIC24HJ32GP202/204 and pic24hj16gp304 3.0-3.6v -40c to +85c 40 3.0-3.6v -40c to +125c 40 table 21-2: thermal operating conditions rating symbol min typ max unit industrial temperature devices operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c extended temperature devices operating junction temperature range t j -40 ? +140 c operating ambient temperature range t a -40 ? +125 c power dissipation: internal chip power dissipation: p int = v dd x (i dd ? i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = ({v dd ? v oh } x i oh ) + (v ol x i ol ) maximum allowed power dissipation p dmax (t j ? t a )/ ja w table 21-3: thermal packaging characteristics characteristic symbol typ max unit notes package thermal resistance, 44-pin qfn ja 62.4 ? c/w 1 package thermal resistance, 44-pin tfqp ja 60 ? c/w 1 package thermal resistance, 28-pin spdip ja 108 ? c/w 1 package thermal resistance, 28-pin soic ja 80.2 ? c/w 1 package thermal resistance, 28-pin qfn-s ja 32 ? c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ja ) numbers are achieved by package simulations.
? 2007 microchip technology inc. preliminary ds70289a-page 195 PIC24HJ32GP202/204 and pic24hj16gp304 table 21-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions operating voltage dc10 supply voltage v dd 3.0 ? 3.6 v industrial and extended dc12 v dr ram data retention voltage (2) 1.1 1.3 1.8 v dc16 v por v dd start voltage to ensure internal power-on reset signal ??v ss v dc17 s vdd v dd rise rate to ensure internal power-on reset signal 0.03 ? ? v/ms 0-3.0v in 0.1s dc18 v core v dd core (3) internal regulator voltage 2.25 ? 2.75 v voltage is dependent on load, temperature and v dd note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: this is the limit to which v dd can be lowered without losing ram data. 3: these parameters are characterized but not tested in manufacturing.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 196 preliminary ? 2007 microchip technology inc. table 21-5: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended parameter no. typical (1) max units conditions operating current (i dd ) (2) dc20d 24 30 ma -40c 3.3v 10 mips dc20a 27 30 ma +25c dc20b 27 30 ma +85c dc20c 27 35 ma +125c dc21d 30 40 ma -40c 3.3v 16 mips dc21a 37 40 ma +25c dc21b 32 45 ma +85c dc21c 33 45 ma +125c dc22d 35 50 ma -40c 3.3v 20 mips dc22a 38 50 ma +25c dc22b 38 55 ma +85c dc22c 39 55 ma +125c dc23d 47 70 ma -40c 3.3v 30 mips dc23a 48 70 ma +25c dc23b 48 70 ma +85c dc23c 48 70 ma +125c dc24d 56 90 ma -40c 3.3v 40 mips dc24a 56 90 ma +25c dc24b 54 90 ma +85c dc24c 54 80 ma +125c 3.3v 35 mips note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements are as follows: osc1 driven with external square wave from rail to rail. all i/o pins are configured as inputs and pulled to v ss . mclr = v dd , wdt and fscm are disabled. cpu, sram, program memory and data memory are operational. no peripheral modules are operating; however, every peripheral is being clocked (pmd bits are all zeroed).
? 2007 microchip technology inc. preliminary ds70289a-page 197 PIC24HJ32GP202/204 and pic24hj16gp304 table 21-6: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended parameter no. typical (1) max units conditions idle current (i idle ): core off clock on base current (2) dc40d 3 25 ma -40c 3.3v 10 mips dc40a 3 25 ma +25c dc40b 3 25 ma +85c dc40c 3 25 ma +125c dc41d 4 25 ma -40c 3.3v 16 mips dc41a 4 ma +25c 25 dc41b 5 25 ma +85c dc41c 5 25 ma +125c dc42d 6 25 ma -40c 3.3v 20 mips dc42a 6 25 ma +25c dc42b 7 25 ma +85c dc42c 7 25 ma +125c dc43d 9 25 ma -40c 3.3v 30 mips dc43a 9 25 ma +25c dc43b 9 25 ma +85c dc43c 9 25 ma +125c dc44d 10 25 ma -40c 3.3v 40 mips dc44a 10 25 ma +25c dc44b 16 25 ma +85c dc44c 10 25 ma +125c 3.3v 35 mips note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. 2: base i idle current is measured with core off, clock on and all modules turned off. peripheral module disable sfr registers are zeroed. all i/o pins are configured as inputs and pulled to v ss .
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 198 preliminary ? 2007 microchip technology inc. table 21-7: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended parameter no. typical (1) max units conditions power-down current (i pd ) (2) dc60d 55 500 a-40c 3.3v base power-down current (3,4) dc60a 63 500 a+25c dc60b 85 500 a+85c dc60c 146 1 ma +125c dc61d 8 12 a-40c 3.3v watchdog timer current: i wdt (3) dc61a 10 15 a+25c dc61b 12 20 a+85c dc61c 13 25 a +125c note 1: data in the typical column is at 3.3v, 25c unless otherwise stated. 2: base i pd is measured with all peripherals and clocks shut down. all i/os are configured as inputs and pulled to v ss . wdt, etc., are all switched off. 3: the current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: these currents are measured on the device containing the most memory in this family. table 21-8: dc characteristics: doze current (i doze ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended parameter no. typical (1) max doze ratio units conditions dc73a 25 32 1:2 ma -40c 3.3v 40 mips dc73f 23 27 1:64 ma dc73g 23 26 1:128 ma dc70a 42 47 1:2 ma +25c 3.3v 40 mips dc70f 26 27 1:64 ma dc70g 25 27 1:128 ma dc71a 41 48 1:2 ma +85c 3.3v 40 mips dc71f 25 28 1:64 ma dc71g 24 28 1:128 ma dc72a 42 49 1:2 ma +125c 3.3v 35 mips dc72f 26 29 1:64 ma dc72g 25 28 1:128 ma note 1: data in the typical column is at 3.3v, 25c unless otherwise stated.
? 2007 microchip technology inc. preliminary ds70289a-page 199 PIC24HJ32GP202/204 and pic24hj16gp304 table 21-9: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions v il input low voltage di10 i/o pins v ss ?0.2v dd v di15 mclr v ss ?0.2v dd v di16 osc1 (xt mode) v ss ?0.2v dd v di17 osc1 (hs mode) v ss ?0.2v dd v di18 sdax, sclx v ss ? 0.3 v dd v smbus disabled di19 sdax, sclx v ss ? 0.2 v dd v smbus enabled v ih input high voltage di20 i/o pins: with analog functions digital-only 0.8 v dd 0.8 v dd ? ? v dd 5.5 v v di25 mclr 0.8 v dd ?v dd v di26 osc1 (xt mode) 0.7 v dd ?v dd v di27 osc1 (hs mode) 0.7 v dd ?v dd v di28 sdax, sclx 0.7 v dd ?v dd v smbus disabled di29 sdax, sclx 0.8 v dd ?v dd v smbus enabled i cnpu cnx pull-up current di30 50 250 400 av dd = 3.3v, v pin = v ss i il input leakage current (2)(3) di50 i/o ports ? ? 2 av ss v pin v dd , pin at high-impedance di51 analog input pins ? ? 1 av ss v pin v dd , pin at high-impedance, 40c t a +85c di51a analog input pins ? ? 2 a analog pins shared with external reference pins, 40c t a +85c di51b analog input pins ? ? 3.5 av ss v pin v dd , pin at high-impedance, -40c t a +125c di51c analog input pins ? ? 8 a analog pins shared with external reference pins, -40c t a +125c di55 mclr ??2 av ss v pin v dd di56 osc1 ? ? 2 av ss v pin v dd , xt and hs modes note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 200 preliminary ? 2007 microchip technology inc. table 21-10: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ max units conditions v ol output low voltage do10 i/o ports ? ? 0.4 v i ol = 2ma, v dd = 3.3v do16 osc2/clko ? ? 0.4 v i ol = 2ma, v dd = 3.3v v oh output high voltage do20 i/o ports 2.40 ? ? v i oh = -2.3 ma, v dd = 3.3v do26 osc2/clko 2.41 ? ? v i oh = -1.3 ma, v dd = 3.3v table 21-11: electrical characteristics: bor dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min (1) typ max units conditions bo10 v bor bor event on v dd transition high-to-low bor event is tied to v dd core voltage decrease 2.40 ? 2.55 v note 1: parameters are for design guidance only and are not tested in manufacturing.
? 2007 microchip technology inc. preliminary ds70289a-page 201 PIC24HJ32GP202/204 and pic24hj16gp304 table 21-13: internal voltag e regulator specifications table 21-12: dc characteristics: program memory dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions program flash memory d130 e p cell endurance 10,000 ? ? e/w -40 c to +125 c d131 v pr v dd for read v min ?3.6vv min = minimum operating voltage d132b v pew v dd for self-timed write v min ?3.6vv min = minimum operating voltage d134 t retd characteristic retention 20 ? ? year provided no other specifications are violated, -40 c to +125 c d135 i ddp supply current during programming ?10 ?ma d136 t rw row write time ? 1.6 ? ms d137 t pe page erase time ? 20 ? ms d138 t ww word write cycle time 20 ? 40 s note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. operating conditions: -40c < t a < +85c (unless otherwise stated) param no. symbol characteristics min typ max units comments c efc external filter capacitor value 110? f capacitor must be low series resistance (< 5 ohms)
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 202 preliminary ? 2007 microchip technology inc. 21.2 ac characteristics and timing parameters the information contained in this section defines PIC24HJ32GP202/204 and pic24hj16gp304 ac characteristics and timing parameters. table 21-14: temperature and vo ltage specifications ? ac figure 21-1: load conditions for device timing specifications table 21-15: capacitiv e loading requirements on output pins ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in section 21.0 ?electrical characteristics? . param no. symbol characteristic min typ max units conditions do50 c osc 2 osc2/sosc2 pin ? ? 15 pf in xt and hs modes when external clock is used to drive osc1 do56 c io all i/o pins and osc2 ? ? 50 pf ec mode do58 c b sclx, sdax ? ? 400 pf in i 2 c? mode v dd /2 c l r l pin pin v ss v ss c l r l = 464 c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 ? for all pins except osc2 load condition 2 ? for osc2
? 2007 microchip technology inc. preliminary ds70289a-page 203 PIC24HJ32GP202/204 and pic24hj16gp304 figure 21-2: external clock timing table 21-16: external clo ck timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symb characteristic min typ (1) max units conditions os10 f in external clki frequency (external clocks allowed only in ec and ecpll modes) dc ? 40 mhz ec oscillator crystal frequency 3.5 10 ? ? ? 10 40 33 mhz mhz khz xt hs sosc os20 t osc t osc = 1/f osc 12.5 ? dc ns os25 t cy instruction cycle time (2) 25 ? dc ns os30 tosl, to s h external clock in (osc1) high or low time 0.375 x t osc ? 0.625 x t osc ns ec os31 tosr, to s f external clock in (osc1) rise or fall time ? ? 20 ns ec os40 tckr clko rise time (3) ?5.2?ns os41 tckf clko fall time (3) ?5.2?ns note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: instruction cycle period (t cy ) equals two times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits can result in an unstable oscillator operation and/or higher than expected current consumpt ion. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. 3: measurements are taken in ec mode. the clko signal is measured on the osc2 pin. q1 q2 q3 q4 osc1 clko q1 q2 q3 q4 os20 os25 os30 os30 os40 os41 os31 os31
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 204 preliminary ? 2007 microchip technology inc. table 21-17: pll clock ti ming specifications (v dd = 3.0v to 3.6v) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions os50 f plli pll voltage controlled oscillator (vco) input frequency range 0.8 ? 8 mhz ecpll, xtpll modes os51 f sys on-chip vco system frequency 100 ? 200 mhz os52 t lock pll start-up time (lock time) 0.9 1.5 3.1 ms os53 d clk clko stability (jitter) -3 0.5 3 % measured over 100 ms period note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. table 21-18: ac characteristics: internal rc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. characteristic min typ max units conditions internal frc accuracy @ frc frequency = 7.37 mhz (1,2) f20 frc -2 ? +2 % -40c t a +85c v dd = 3.0-3.6v frc -5 ? +5 % -40c t a +125c v dd = 3.0-3.6v note 1: frequency calibrated at 25c and 3.3v. tun bits can be used to compensate for temperature drift. 2: frc is set to initial frequency of 7.37 mhz (2%) at 25c. table 21-19: internal rc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. characteristic min typ max units conditions lprc @ 32.768 khz (1) f21 lprc -20 6 +20 % -40c t a +85c v dd = 3.0-3.6v lprc -70 ? +20 % -40c t a +125c v dd = 3.0-3.6v note 1: change of lprc frequency as v dd changes.
? 2007 microchip technology inc. preliminary ds70289a-page 205 PIC24HJ32GP202/204 and pic24hj16gp304 figure 21-3: i/o timing characteristics table 21-20: i/o timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions do31 t io r port output rise time ? 10 25 ns ? do32 t io f port output fall time ? 10 25 ns ? di35 t inp intx pin high or low time (output) 20 ? ? ns ? di40 t rbp cnx high or low time (input) 2 ? ? t cy ? note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. note: refer to figure 21-1 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 206 preliminary ? 2007 microchip technology inc. figure 21-4: reset, watchdog timer, os cillator start-up timer and power-up timer timing characteristics v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset sy11 sy10 sy20 sy13 i/o pins sy13 note: refer to figure 21-1 for load conditions. fscm delay sy35 sy30 sy12
? 2007 microchip technology inc. preliminary ds70289a-page 207 PIC24HJ32GP202/204 and pic24hj16gp304 table 21-21: reset, watchdog timer, oscill ator start-up timer, power-up timer timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sy10 t mc lmclr pulse width (low) 2 ? ? s -40c to +85c sy11 t pwrt power-up timer period ? 2 4 8 16 32 64 128 ? ms -40c to +85c user programmable sy12 t por power-on reset delay 3 10 30 s -40c to +85c sy13 t ioz i/o high-impedance from mclr low or watchdog timer reset 0.68 0.72 1.2 s sy20 t wdt 1 watchdog timer time-out period (no prescaler) 1.7 2.1 2.6 ms v dd = 3v, -40c to +85c sy30 t ost oscillator start-up time ? 1024 t osc ??t osc = osc1 period sy35 t fscm fail-safe clock monitor delay ? 500 900 s -40c to +85c note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 208 preliminary ? 2007 microchip technology inc. figure 21-5: timer1, 2 and 3 external cl ock timing characteristics table 21-22: timer1 external clock timing requirements (1) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ max units conditions ta10 t tx h txck high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter ta15 synchronous, with prescaler 10 ? ? ns asynchronous 10 ? ? ns ta11 t tx l txck low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter ta15 synchronous, with prescaler 10 ? ? ns asynchronous 10 ? ? ns ta15 t tx p txck input period synchronous, no prescaler t cy + 40 ? ? ns synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n ???n = prescale value (1, 8, 64, 256) asynchronous 20 ? ? ns os60 ft1 sosc1/t1ck oscillator input frequency range (oscillator enabled by setting bit tcs (t1con<1>)) dc ? 50 khz ta20 t ckextmrl delay from external txck clock edge to timer increment 0.5 t cy 1.5 t cy ? note 1: timer1 is a type a. note: refer to figure 21-1 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck
? 2007 microchip technology inc. preliminary ds70289a-page 209 PIC24HJ32GP202/204 and pic24hj16gp304 table 21-23: timer2 external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ max units conditions tb10 ttxh txck high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter tb15 synchronous, with prescaler 10 ? ? ns tb11 ttxl txck low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter tb15 synchronous, with prescaler 10 ? ? ns tb15 ttxp txck input period synchronous, no prescaler t cy + 40 ? ? ns n = prescale value (1, 8, 64, 256) synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n tb20 t ckext - mrl delay from external txck clock edge to timer increment 0.5 t cy ? 1.5 t cy ? table 21-24: timer3 external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ max units conditions tc10 ttxh txck high time synchronous 0.5 t cy + 20 ? ? ns must also meet parameter tc15 tc11 ttxl txck low time synchronous 0.5 t cy + 20 ? ? ns must also meet parameter tc15 tc15 ttxp txck input period synchronous, no prescaler t cy + 40 ? ? ns n = prescale value (1, 8, 64, 256) synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n tc20 t ckext - mrl delay from external txck clock edge to timer increment 0.5 t cy ?1.5 t cy ?
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 210 preliminary ? 2007 microchip technology inc. figure 21-6: input capture (capx) timing characteristics figure 21-7: output compare module (o cx) timing characteristics table 21-25: input capture timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min max units conditions ic10 tccl icx input low time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns ic11 tcch icx input high time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns ic15 tccp icx input period (t cy + 40)/n ? ns n = prescale value (1, 4, 16) note 1: these parameters are characterized but not tested in manufacturing. table 21-26: output compare module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions oc10 tccf ocx output fall time ? ? ? ns see parameter d032 oc11 tccr ocx output rise time ? ? ? ns see parameter d031 note 1: these parameters are characterized but not tested in manufacturing. icx ic10 ic11 ic15 note: refer to figure 21-1 for load conditions. ocx oc11 oc10 (output compare note: refer to figure 21-1 for load conditions. or pwm mode)
? 2007 microchip technology inc. preliminary ds70289a-page 211 PIC24HJ32GP202/204 and pic24hj16gp304 figure 21-8: oc/pwm module ti ming characteristics table 21-27: simple oc/pwm mode timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions oc15 t fd fault input to pwm i/o change ? ? 50 ns ? oc20 t flt fault input pulse width 50 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. ocfa/ocfb ocx oc20 oc15
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 212 preliminary ? 2007 microchip technology inc. figure 21-9: spix module master mode (cke = 0 ) timing characteristics sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp11 sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30 sp31 note: refer to figure 21-1 for load conditions. table 21-28: spix master mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscl sckx output low time t cy /2 ? ? ns see note 3 sp11 tsch sckx output high time t cy /2 ? ? ns see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter d032 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter d031 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter d032 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter d031 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 23 ? ? ns ? sp41 tsch2dil, ts c l 2 d i l hold time of sdix data input to sckx edge 30 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 100 ns. therefore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins.
? 2007 microchip technology inc. preliminary ds70289a-page 213 PIC24HJ32GP202/204 and pic24hj16gp304 figure 21-10: spix module master mode (cke = 1 ) timing characteristics table 21-29: spix module master mode (cke = 1 ) timing requirements sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi x sp36 sp30,sp31 sp35 msb msb in bit 14 - - - - - -1 lsb in bit 14 - - - -1 lsb note: refer to figure 21-1 for load conditions. sp11 sp10 sp20 sp21 sp21 sp20 sp40 sp41 ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscl sckx output low time t cy /2 ? ? ns see note 3 sp11 tsch sckx output high time t cy /2 ? ? ns see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter d032 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter d031 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter d032 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter d031 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns ? sp36 tdov2sc, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 23 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 100 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 214 preliminary ? 2007 microchip technology inc. figure 21-11: spix modul e slave mode (cke = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp70 note: refer to figure 21-1 for load conditions. sdi x table 21-30: spix modul e slave mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscl sckx input low time 30 ? ? ns ? sp71 tsch sckx input high time 30 ? ? ns ? sp72 tscf sckx input fall time ? 10 25 ns see note 3 sp73 tscr sckx input rise time ? 10 25 ns see note 3 sp30 tdof sdox data output fall time ? ? ? ns see parameter d032 and note 3 sp31 tdor sdox data output rise time ? ? ? ns see parameter d031 and note 3 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? ? 30 ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 20 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 20 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance 10 ? 50 ns see note 3 sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy +40 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: assumes 50 pf load on all spix pins.
? 2007 microchip technology inc. preliminary ds70289a-page 215 PIC24HJ32GP202/204 and pic24hj16gp304 figure 21-12: spix modul e slave mode (cke = 1 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp50 sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp52 sp73 sp72 sp72 sp73 sp71 sp70 sp40 sp41 note: refer to figure 21-1 for load conditions.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 216 preliminary ? 2007 microchip technology inc. table 21-31: spix modul e slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscl sckx input low time 30 ? ? ns ? sp71 tsch sckx input high time 30 ? ? ns ? sp72 tscf sckx input fall time ? 10 25 ns see note 3 sp73 tscr sckx input rise time ? 10 25 ns see note 3 sp30 tdof sdox data output fall time ? ? ? ns see parameter d032 and note 3 sp31 tdor sdox data output rise time ? ? ? ns see parameter d031 and note 3 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ??30ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 20 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 20 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdo x output high-impedance 10 ? 50 ns see note 4 sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns ? sp60 tssl2dov sdox data output valid after ssx edge ??50ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 100 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins.
? 2007 microchip technology inc. preliminary ds70289a-page 217 PIC24HJ32GP202/204 and pic24hj16gp304 figure 21-13: i2cx bus start/stop bits ti ming characteristics (master mode) figure 21-14: i2cx bus data timing characteristics (master mode) im31 im34 sclx sdax start condition stop condition im30 im33 note: refer to figure 21-1 for load conditions. im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 21-1 for load conditions.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 218 preliminary ? 2007 microchip technology inc. table 21-32: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min (1) max units conditions im10 t lo : scl clock low time 100 khz mode t cy /2 (brg + 1) ? s? 400 khz mode t cy /2 (brg + 1) ? s? 1 mhz mode (2) t cy /2 (brg + 1) ? s? im11 t hi : scl clock high time 100 khz mode t cy /2 (brg + 1) ? s? 400 khz mode t cy /2 (brg + 1) ? s? 1 mhz mode (2) t cy /2 (brg + 1) ? s? im20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ? 100 ns im21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ? 300 ns im25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (2) 40 ? ns im26 t hd : dat data input hold time 100 khz mode 0 ? s? 400 khz mode 0 0.9 s 1 mhz mode (2) 0.2 ? s im30 t su : sta start condition setup time 100 khz mode t cy /2 (brg + 1) ? s only relevant for repeated start condition 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode (2) t cy /2 (brg + 1) ? s im31 t hd : sta start condition hold time 100 khz mode t cy /2 (brg + 1) ? s after this period the first clock pulse is generated 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode (2) t cy /2 (brg + 1) ? s im33 t su : sto stop condition setup time 100 khz mode t cy /2 (brg + 1) ? s? 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode (2) t cy /2 (brg + 1) ? s im34 t hd : sto stop condition 100 khz mode t cy /2 (brg + 1) ? ns ? hold time 400 khz mode t cy /2 (brg + 1) ? ns 1 mhz mode (2) t cy /2 (brg + 1) ? ns im40 t aa : scl output valid from clock 100 khz mode ? 3500 ns ? 400 khz mode ? 1000 ns ? 1 mhz mode (2) ? 400 ns ? im45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (2) 0.5 ? s im50 c b bus capacitive loading ? 400 pf note 1: brg is the value of the i 2 c baud rate generator. refer to section 19. ?inter-integrated circuit (i2c?)? in the ?pic24h family reference manual?. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only).
? 2007 microchip technology inc. preliminary ds70289a-page 219 PIC24HJ32GP202/204 and pic24hj16gp304 figure 21-15: i2cx bus start/stop bits timing characteristics (slave mode) figure 21-16: i2cx bus data timing characteristics (slave mode) is31 is34 sclx sdax start condition stop condition is30 is33 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 sclx sdax in sdax out
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 220 preliminary ? 2007 microchip technology inc. table 21-33: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param symbol characteristic min max units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s device must operate at a minimum of 10 mhz 1 mhz mode (1) 0.5 ? s? is11 t hi : scl clock high time 100 khz mode 4.0 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s device must operate at a minimum of 10 mhz 1 mhz mode (1) 0.5 ? s? is20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 100 ns is21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 300 ns is25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (1) 100 ? ns is26 t hd : dat data input hold time 100 khz mode 0 0 s? 400 khz mode 0 0.9 s 1 mhz mode (1) 00.3 s is30 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 1 mhz mode (1) 0.25 ? s is31 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 1 mhz mode (1) 0.25 ? s is33 t su : sto stop condition setup time 100 khz mode 4.7 ? s? 400 khz mode 0.6 ? s 1 mhz mode (1) 0.6 ? s is34 t hd : st o stop condition hold time 100 khz mode 4000 ? ns ? 400 khz mode 600 ? ns 1 mhz mode (1) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns ? 400 khz mode 0 1000 ns 1 mhz mode (1) 0 350 ns is45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (1) 0.5 ? s is50 c b bus capacitive loading ? 400 pf ? note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only).
? 2007 microchip technology inc. preliminary ds70289a-page 221 PIC24HJ32GP202/204 and pic24hj16gp304 table 21-34: adc mo dule specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions device supply ad01 av dd module v dd supply greater of v dd ? 0.3 or 3.0 ? lesser of v dd + 0.3 or 3.6 v ? ad02 av ss module v ss supply v ss ? 0.3 ? v ss + 0.3 v ? reference inputs ad05 v refh reference voltage high av ss + 2.7 ? av dd vsee note 1 ad05a 3.0 ? 3.6 v v refh = av dd v refl = av ss = 0 ad06 v refl reference voltage low av ss ?av dd ? 2.7 v see note 1 ad06a 0 ? 0 v v refh = av dd v refl = av ss = 0 ad07 v ref absolute reference voltage 2.7 ? 3.6 v v ref = v refh - v refl ad08 i ref current drain ? 400 ? 550 10 a a adc operating adc off analog input ad12 v inh input voltage range v inh v inl ?v refh v this voltage reflects sample and hold channels 0, 1, 2, and 3 (ch0-ch3), positive input ad13 v inl input voltage range v inl v refl ?av ss + 1v v this voltage reflects sample and hold channels 0, 1, 2, and 3 (ch0-ch3), negative input ad17 r in recommended impedance of analog voltage source ? ? ? ? 200 200 10-bit adc 12-bit adc note 1: these parameters are not characterized or tested in manufacturing.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 222 preliminary ? 2007 microchip technology inc. table 21-35: adc module speci fications (12-bit mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions adc accuracy (12-bit mode) ? measurements with external v ref +/v ref - ad20a nr resolution 12 data bits bits ad21a inl integral nonlinearity -2 ? +2 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad22a dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad23a g err gain error 1.25 1.5 3 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad24a e off offset error 1.25 1.52 2 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad25a ? monotonicity ? ? ? ? guaranteed adc accuracy (12-bit mode) ? measurements with internal v ref +/v ref - ad20a nr resolution 12 data bits bits ad21a inl integral nonlinearity -2 ? +2 lsb v inl = av ss = 0v, av dd = 3.6v ad22a dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = 0v, av dd = 3.6v ad23a g err gain error 2 3 7 lsb v inl = av ss = 0v, av dd = 3.6v ad24a e off offset error 2 3 5 lsb v inl = av ss = 0v, av dd = 3.6v ad25a ? monotonicity ? ? ? ? guaranteed dynamic performance (12-bit mode) ad30a thd total harmonic distortion -77 -69 -61 db ? ad31a sinad signal to noise and distortion 59 63 64 db ? ad32a sfdr spurious free dynamic range 63 72 74 db ? ad33a f nyq input signal bandwidth ? ? 250 khz ? ad34a enob effective number of bits 10.95 11.1 ? bits ?
? 2007 microchip technology inc. preliminary ds70289a-page 223 PIC24HJ32GP202/204 and pic24hj16gp304 table 21-36: adc module speci fications (10-bit mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions adc accuracy (10-bit mode) ? measurements with external v ref +/v ref - ad20b nr resolution 10 data bits bits ad21b inl integral nonlinearity -1.5 ? +1.5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad22b dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad23b g err gain error 1 3 6 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad24b e off offset error 1 2 5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad25b ? monotonicity ? ? ? ? guaranteed adc accuracy (10-bit mode) ? measurements with internal v ref +/v ref - ad20b nr resolution 10 data bits bits ad21b inl integral nonlinearity -1 ? +1 lsb v inl = av ss = 0v, av dd = 3.6v ad22b dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = 0v, av dd = 3.6v ad23b g err gain error 1 5 6 lsb v inl = av ss = 0v, av dd = 3.6v ad24b e off offset error 1 2 3 lsb v inl = av ss = 0v, av dd = 3.6v ad25b ? monotonicity ? ? ? ? guaranteed dynamic performance (10-bit mode) ad30b thd total harmonic distortion ? -64 -67 db ? ad31b sinad signal to noise and distortion ?5758db ? ad32b sfdr spurious free dynamic range ?6062db ? ad33b f nyq input signal bandwidth ? ? 550 khz ? ad34b enob effective number of bits 9.1 9.7 9.8 bits ?
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 224 preliminary ? 2007 microchip technology inc. figure 21-17: adc conversion (12- bit mode) timing characteristics (asam = 0 , ssrc<2:0> = 000 ) table 21-37: adc conversion (12-bi t mode) timing requirements ad55 t samp clear samp set samp ad61 adclk instruction samp ad60 done ad1if 1 2 3 4 5 6 8 7 1 ? software sets ad1con. samp to start sampling. 2 ? sampling starts after discharge period. t samp is described in 3 ? software clears ad1con. samp to start conversion. 4 ? sampling ends, conversion sequence starts. 5 ? convert bit 11 . 9 ? one t ad for end of conversion. ad50 9 6 ? convert bit 10 . 7 ? convert bit 1 . 8 ? convert bit 0 . execution section 28. ?10/12-bit adc without dma? in the ?pic24h family reference manual? . ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions clock parameters ad50 t ad adc clock period 117.6 ? ? ns ad51 t rc adc internal rc oscillator period ? 250 ? ns conversion rate ad55 t conv conversion time ? 14 t ad ns ad56 f cnv throughput rate ? ? 500 ksps ad57 t samp sample time 3 t ad ?? ? timing parameters ad60 t pcs conversion start from sample trigger (2) ?1.0 t ad ? ? auto convert trigger not selected ad61 t pss sample start from setting sample (samp) bit (2) 0.5 t ad ? 1.5 t ad ?? ad62 t css conversion completion to sample start (asam = 1 ) (2) ?0.5 t ad ?? ? ad63 t dpu time to stabilize analog stage from adc off to adc on (2) 1?5 s? note 1: because the sample caps will eventually lose charge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures. 2: these parameters are characterized but not tested in manufacturing.
? 2007 microchip technology inc. preliminary ds70289a-page 225 PIC24HJ32GP202/204 and pic24hj16gp304 figure 21-18: adc conversion (10- bit mode) timing characteristics (chps<1:0> = 01 , simsam = 0 , asam = 0 , ssrc<2:0> = 000 ) figure 21-19: adc conversion (10-bit mode) timing characteristics (chps<1:0> = 01 , simsam = 0 , asam = 1 , ssrc<2:0> = 111 , samc<4:0> = 00001 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ad60 done ad1if buffer( 0 ) buffer( 1 ) 1 2 3 4 5 6 8 5 6 7 1 ? software sets ad1con. samp to start sampling. 2 ? sampling starts after discharge period. t samp is described in 3 ? software clears ad1con. samp to start conversion. 4 ? sampling ends, conversion sequence starts. 5 ? convert bit 9. 8 ? one t ad for end of conversion. ad50 7 ad55 8 6 ? convert bit 8. 7 ? convert bit 0. execution ?pic24h family reference manual? . section 28. ?10/12-bit adc without dma? in the 1 2 3 4 5 6 4 5 6 8 1 ? software sets ad1con. adon to start ad operation. 2 ? sampling starts after discharge period. t samp is described in 3 ? convert bit 9. 4 ? convert bit 8. 5 ? convert bit 0. 7 3 6 ? one t ad for end of conversion. 7 ? begin conversion of next channel. 8 ? sample for time specified by samc<4:0>. section 28. ?10/12-bit adc without dma? in the adclk instruction set adon execution samp t samp ad1if done ad55 ad55 t samp ad55 ad50 ?pic24h family reference manual?.
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 226 preliminary ? 2007 microchip technology inc. table 21-38: adc conversion (10-bi t mode) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ (1) max. units conditions clock parameters ad50 t ad adc clock period 76 ? ? ns ad51 t rc adc internal rc oscillator period ? 250 ? ns conversion rate ad55 t conv conversion time ? 12 t ad ?? ad56 f cnv throughput rate ? ? 1.1 msps ad57 t samp sample time 2 t ad ??? timing parameters ad60 t pcs conversion start from sample trigger (1) ?1.0 t ad ? ? auto-convert trigger not selected ad61 t pss sample start from setting sample (samp) bit (1) 0.5 t ad ? 1.5 t ad ?? ad62 t css conversion completion to sample start (asam = 1 ) (1) ?0.5 t ad ?? ? ad63 t dpu time to stabilize analog stage from adc off to adc on (1) 1?5 s? note 1: these parameters are characterized but not tested in manufacturing. 2: because the sample caps will eventually lose charge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures.
? 2007 microchip technology inc. preliminary ds70289a-page 227 PIC24HJ32GP202/204 and pic24hj16gp304 22.0 packaging information 22.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : if the full microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn example pic24hj 32gp204 -e/pt 0730235 3 e pic24hj32 gp204-e/ml 0730235 3 e 3 e 28-lead spdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example PIC24HJ32GP202-i/sp 0610017 28-lead soic (.300?) xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example PIC24HJ32GP202/so 0610017 3 e 3 e xxxxxxxx 28-lead qfn-s xxxxxxxx yywwnnn 24hj32gp example 202e/mm 0730235
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 228 preliminary ? 2007 microchip technology inc. 22.2 package details 28-lead skinny plastic dual in-line (sp) ? 300 mil body [spdip] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 28 pitch e .100 bsc top to seating plane a ? ? .200 molded package thickness a2 .120 .135 .150 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .335 molded package width e1 .240 .285 .295 overall length d 1.345 1.365 1.400 tip to seating plane l .110 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .050 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 note 1 n 12 d e1 e b c e l a2 e b b1 a1 a 3 microchip technology drawing c04-070 b
? 2007 microchip technology inc. preliminary ds70289a-page 229 PIC24HJ32GP202/204 and pic24hj16gp304 28-lead plastic small outline (so) ? wide, 7.50 mm body [soic] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millmeters dimension limits min nom max number of pins n 28 pitch e 1.27 bsc overall height a ? ? 2.65 molded package thickness a2 2.05 ? ? standoff a1 0.10 ? 0.30 overall width e 10.30 bsc molded package width e1 7.50 bsc overall length d 17.90 bsc chamfer (optional) h 0.25 ? 0.75 foot length l 0.40 ? 1.27 footprint l1 1.40 ref foot angle top 0 ? 8 lead thickness c 0.18 ? 0.33 lead width b 0.31 ? 0.51 mold draft angle top 5 ? 15 mold draft angle bottom 5 ? 15 c h h l l1 a2 a1 a note 1 12 3 b e e e1 d n microchip technology drawing c04-052 b
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 230 preliminary ? 2007 microchip technology inc. 28-lead plastic quad flat, no lead package (mm) ? 6x6x0.9 mm body [qfn-s] with 0.40 mm contact length notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package is saw singulated. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 0.65 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall width e 6.00 bsc exposed pad width e2 3.65 3.70 4.70 overall length d 6.00 bsc exposed pad length d2 3.65 3.70 4.70 contact width b 0.23 0.38 0.43 contact length l 0.30 0.40 0.50 contact-to-exposed pad k 0.20 ? ? d e 2 1 n e2 exposed pad 2 1 d2 n e b k l note 1 a 3 a a1 top view bottom view microchip technology drawing c04-124b
? 2007 microchip technology inc. preliminary ds70289a-page 231 PIC24HJ32GP202/204 and pic24hj16gp304 44-lead plastic quad flat, no lead package (ml) ? 8x8 mm body [qfn] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . package is saw singulated. 3 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 44 pitch e 0.65 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall width e 8.00 bsc exposed pad width e2 6.30 6.45 6.80 overall length d 8.00 bsc exposed pad length d2 6.30 6.45 6.80 contact width b 0.25 0.30 0.38 contact length l 0.30 0.40 0.50 contact-to-exposed pad k 0.20 ? ? d exposed pad d2 e b k l e2 2 1 n note 1 2 1 e n bottom view top view a 3 a1 a microchip technology drawing c04-103 b
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 232 preliminary ? 2007 microchip technology inc. 44-lead plastic thin quad flatpack (pt) ? 10x10x1 mm body, 2.00 mm footprint [tqfp] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. chamfers at corners are optional; size may vary. 3. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of leads n 44 lead pitch e 0.80 bsc overall height a ? ? 1.20 molded package thickness a2 0.95 1.00 1.05 standoff a1 0.05 ? 0.15 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 3.5 7 overall width e 12.00 bsc overall length d 12.00 bsc molded package width e1 10.00 bsc molded package length d1 10.00 bsc lead thickness c 0.09 ? 0.20 lead width b 0.30 0.37 0.45 mold draft angle top 11 12 13 mold draft angle bottom 11 12 13 a e e1 d d1 e b note 1 note 2 n 12 3 c a1 l a2 l1 microchip technology drawing c04-076 b
? 2007 microchip technology inc. preliminary ds70289a-page 233 PIC24HJ32GP202/204 and pic24hj16gp304 appendix a: revision history revision a (august 2007) initial release of this document
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 234 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70289a-page 235 PIC24HJ32GP202/204 and pic24hj16gp304 index a a/d converter ................................................................... 159 initialization ............................................................... 159 key features............................................................. 159 ac characteristics ............................................................ 202 internal rc accuracy ................................................ 204 load conditions ........................................................ 202 adc module adc11 register map ...................................... 28, 30, 31 alternate vector table (aivt)............................................. 53 arithmetic logic unit (alu)................................................. 18 assembler mpasm assembler................................................... 190 automatic clock stretch.................................................... 143 receive mode ........................................................... 143 transmit mode .......................................................... 143 b block diagrams 16-bit timer1 module ................................................ 117 a/d module ....................................................... 160, 161 connections for on-chip voltage regulator............. 176 device clock ......................................................... 81, 83 input capture ............................................................ 125 output compare ....................................................... 130 pic24h ....................................................................... 10 pic24h cpu core ...................................................... 14 pll.............................................................................. 83 reset system.............................................................. 47 shared port structure ................................................. 93 spi ............................................................................ 134 timer2 (16-bit) .......................................................... 121 timer2/3 (32-bit) ....................................................... 120 uart ........................................................................ 151 watchdog timer (wdt) ............................................ 177 c c compilers mplab c18 .............................................................. 190 mplab c30 .............................................................. 190 clock switching................................................................... 89 enabling ...................................................................... 89 sequence.................................................................... 89 code examples erasing a program memory page............................... 45 initiating a programming sequence............................ 46 loading write buffers ................................................. 46 port write/read .......................................................... 94 pwrsav instruction syntax....................................... 91 code protection ........................................................ 173, 178 configuration bits.............................................................. 173 description (table).................................................... 174 configuration register map .............................................. 173 configuring analog port pins.............................................. 94 cpu control register .......................................................... 16 cpu clocking system......................................................... 82 options........................................................................ 82 selection ..................................................................... 82 customer change notification service ............................. 238 customer notification service........................................... 238 customer support............................................................. 238 d data address space........................................................... 21 alignment.................................................................... 21 memory map for pic24h devices with 8 kbs ram ... 22 near data space ........................................................ 21 software stack ........................................................... 34 width .......................................................................... 21 dc characteristics............................................................ 194 i/o pin input specifications ...................................... 199 i/o pin output specifications.................................... 200 idle current (i doze ) .................................................. 198 idle current (i idle ) .................................................... 197 operating current (i dd ) ............................................ 196 power-down current (i pd )........................................ 198 program memory...................................................... 201 temperature and voltage specifications.................. 195 development support ....................................................... 189 e electrical characteristics .................................................. 193 ac............................................................................. 202 equations a/d conversion clock period ................................... 162 calculating the pwm period..................................... 128 calculation for maximum pwm resolution .............. 128 device operating frequency...................................... 82 relationship between device and spi clock speed .............................................. 136 serial clock rate...................................................... 141 uart baud rate with brgh = 0 ............................. 152 uart baud rate with brgh = 1 ............................. 152 errata .................................................................................... 7 f flash program memory ...................................................... 41 control registers........................................................ 42 operations .................................................................. 42 programming algorithm.............................................. 45 rtsp operation ......................................................... 42 table instructions ....................................................... 41 flexible configuration ....................................................... 173 fscm delay for crystal and pll clock sources .................. 51 device resets ............................................................ 51 i i/o ports ............................................................................. 93 parallel i/o (pio) ........................................................ 93 write/read timing...................................................... 94 i 2 c addresses................................................................. 143 baud rate generator ............................................... 141 general call address support.................................. 143 interrupts .................................................................. 141 ipmi support............................................................. 143 master mode operation clock arbitration ............................................... 144 multi-master communication, bus collision and bus arbitration................................... 144 operating modes ...................................................... 141 registers .................................................................. 141 slave address masking ............................................ 143 slope control............................................................ 144
? 2007 microchip technology inc. preliminary ds70289a-page 236 PIC24HJ32GP202/204 and pic24hj16gp304 software controlled clock stretching (stren = 1).. 143 i 2 c module i2c1 register map ...................................................... 27 in-circuit debugger ........................................................... 179 in-circuit emulation........................................................... 173 in-circuit serial programming (icsp) ....................... 173, 179 infrared support built-in irda encoder and decoder........................... 153 external irda, irda clock output.............................. 153 input capture registers................................................................... 126 input change notification.................................................... 94 instruction addressing modes............................................. 34 file register instructions ............................................ 34 fundamental modes supported.................................. 35 mcu instructions ........................................................ 34 move and accumulator instructions............................ 35 other instructions........................................................ 35 instruction set overview ................................................................... 184 summary................................................................... 181 instruction-based power-saving modes ............................. 91 idle .............................................................................. 92 sleep........................................................................... 91 internal rc oscillator use with wdt ........................................................... 177 internet address................................................................ 238 interrupt control and status registers................................ 57 iecx ............................................................................ 57 ifsx............................................................................. 57 intcon1 .................................................................... 57 intcon2 .................................................................... 57 ipcx ............................................................................ 57 interrupt setup procedures ................................................. 79 initialization ................................................................. 79 interrupt disable.......................................................... 79 interrupt service routine ............................................ 79 trap service routine .................................................. 79 interrupt vector table (ivt) ................................................ 53 interrupts coincident with power save instructions............ 92 j jtag boundary scan interface ........................................ 173 m memory organization.......................................................... 19 microchip internet web site .............................................. 238 mplab asm30 assembler, linker, librarian ................... 190 mplab icd 2 in-circuit debugger ................................... 191 mplab ice 2000 high-performance universal in-circuit emulator.................................................................... 191 mplab integrated development environment software .. 189 mplab pm3 device programmer .................................... 191 mplab real ice in-circuit emulator system................. 191 mplink object linker/mplib object librarian ................ 190 multi-bit data shifter ........................................................... 18 n nvm module register map............................................................... 33 o open-drain configuration ................................................... 94 output compare ............................................................... 127 registers................................................................... 131 p packaging ......................................................................... 227 details....................................................................... 228 marking..................................................................... 227 peripheral module disable (pmd) ...................................... 92 picstart plus development programmer..................... 192 pinout i/o descriptions (table)............................................ 11 pmd module register map .............................................................. 33 por and long oscillator start-up times ........................... 51 porta register map .............................................................. 32 portb register map .............................................................. 32 power-saving features ...................................................... 91 clock frequency and switching ................................. 91 program address space..................................................... 19 construction ............................................................... 36 data access from program memory using program space visibility..................................... 39 data access from program memory using table instructions ............................................... 38 data access from, address generation ..................... 37 memory map............................................................... 19 table read instructions tblrdh ............................................................. 38 tblrdl.............................................................. 38 visibility operation...................................................... 39 program memory interrupt vector........................................................... 20 organization ............................................................... 20 reset vector............................................................... 20 pulse-width modulation mode.......................................... 128 pwm duty cycle ................................................................ 128 period ....................................................................... 128 r reader response............................................................. 239 registers ad1chs0 (adc1 input channel 0 select................ 169 ad1chs123 (adc1 input channel 1, 2, 3 select)... 167 ad1con1 (adc1 control 1) .................................... 163 ad1con2 (adc1 control 2) .................................... 165 ad1con3 (adc1 control 3) .................................... 166 ad1cssl (adc1 input scan select low) ............... 171 ad1pcfgl (adc1 port configuration low) ............ 171 clkdiv (clock divisor) .............................................. 86 corcon (core control) ...................................... 17, 59 i2cxcon (i2cx control)........................................... 145 i2cxmsk (i2cx slave mode address mask)............ 149 i2cxstat (i2cx status) ........................................... 147 icxcon (input capture x control)............................ 126 iec0 (interrupt enable control 0) ................... 66, 68, 69 ifs0 (interrupt flag status 0) ..................................... 62 ifs1 (interrupt flag status 1) ..................................... 64 ifs4 (interrupt flag status 4) ..................................... 65 intcon1 (interrupt control 1) ................................... 60 intcon2 (interrupt control 2) ................................... 61 inttreg interrupt control and status register ........ 78 ipc0 (interrupt priority control 0) ............................... 70 ipc1 (interrupt priority control 1) ............................... 71 ipc16 (interrupt priority control 16) ........................... 77 ipc2 (interrupt priority control 2) ............................... 72 ipc3 (interrupt priority control 3) ............................... 73
? 2007 microchip technology inc. preliminary ds70289a-page 237 PIC24HJ32GP202/204 and pic24hj16gp304 ipc4 (interrupt priority control 4) ............................... 74 ipc5 (interrupt priority control 5) ............................... 75 ipc7 (interrupt priority control 7) ............................... 76 nvmcom (flash memory control)....................... 43, 44 ocxcon (output compare x control) ..................... 131 osccon (oscillator control) ..................................... 84 osctun (frc oscillator tuning) .............................. 88 pllfbd (pll feedback divisor)................................ 87 rcon (reset control) ................................................ 48 spixcon1 (spix control 1)...................................... 138 spixcon2 (spix control 2)...................................... 140 spixstat (spix status and control) ....................... 137 sr (cpu status)................................................... 16, 58 t1con (timer1 control)........................................... 118 txcon (t2con, t4con, t6con or t8con control)................................................ 122 tycon (t3con, t5con, t7con or t9con control)................................................ 123 uxmode (uartx mode).......................................... 154 uxsta (uartx status and control)......................... 156 reset clock source selection............................................... 50 special function register reset states ..................... 51 times .......................................................................... 50 reset sequence ................................................................. 53 resets................................................................................. 47 s serial peripheral interface (spi) ....................................... 133 setup for continuous output pulse generation................ 127 setup for single output pulse generation ........................ 127 software simulator (mplab sim)..................................... 190 software stack pointer, frame pointer call stack frame...................................................... 34 special features of the cpu ............................................ 173 spi master, frame master connection ........................... 135 master/slave connection.......................................... 135 slave, frame master connection ............................. 136 slave, frame slave connection ............................... 136 spi module spi1 register map...................................................... 27 symbols used in opcode descriptions............................. 182 t temperature and voltage specifications ac ............................................................................. 202 timer1 ............................................................................... 117 timer2/3, timer4/5, timer6/7 and timer8/9 ..................... 119 timing characteristics clko and i/o ........................................................... 205 timing diagrams 10-bit a/d conversion............................................... 225 10-bit a/d conversion (chps = 01, simsam = 0, asam = 0, ssrc = 000) .................................. 225 12-bit a/d conversion (asam = 0, ssrc = 000) ..... 224 external clock........................................................... 203 i2cx bus data (master mode) .................................. 217 i2cx bus data (slave mode) .................................... 219 i2cx bus start/stop bits (master mode) ................... 217 i2cx bus start/stop bits (slave mode) ..................... 219 input capture (capx)................................................ 210 oc/pwm................................................................... 211 output compare (ocx)............................................. 210 reset, watchdog timer, oscillator start-up timer and power-up timer ................................................ 206 spix master mode (cke = 0) ................................... 212 spix master mode (cke = 1) ................................... 213 spix slave mode (cke = 0) ..................................... 214 spix slave mode (cke = 1) ..................................... 215 timer1, 2, 3, 4, 5, 6, 7, 8, 9 external clock .............. 208 timing requirements clko and i/o ........................................................... 205 external clock .......................................................... 203 input capture............................................................ 210 timing specifications 10-bit a/d conversion requirements ....................... 226 12-bit a/d conversion requirements ....................... 224 i2cx bus data requirements (master mode)........... 218 i2cx bus data requirements (slave mode)............. 220 output compare requirements................................ 210 pll clock ................................................................. 204 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements ................................................... 207 simple oc/pwm mode requirements ..................... 211 spix master mode (cke = 0) requirements............ 212 spix master mode (cke = 1) requirements............ 213 spix slave mode (cke = 0) requirements.............. 214 spix slave mode (cke = 1) requirements.............. 216 timer1 external clock requirements ....................... 208 timer2, timer4, timer6 and timer8 external clock requirements ......................................... 209 timer3, timer5, timer7 and timer9 external clock requirements ......................................... 209 u uart baud rate generator (brg) .............................................. 152 break and sync transmit sequence ........................ 153 flow control using uxcts and uxrts pins ........... 153 receiving in 8-bit or 9-bit data mode ....................... 153 transmitting in 8-bit data mode ............................... 153 transmitting in 9-bit data mode ............................... 153 uart module uart1 register map ................................................. 27 v voltage regulator (on-chip) ............................................ 176 w watchdog timer (wdt)............................................ 173, 177 programming considerations ................................... 177 www address ................................................................. 238 www, on-line support ..................... .................................. 7
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 238 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds70289a-page 239 PIC24HJ32GP202/204 and pic24hj16gp304 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following informa- tion: ? product support ? data sheets and errata, appli- cation notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of micro- chip sales offices, distributors and factory repre- sentatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notifi- cation and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representa- tive or field application engineer (fae) for support. local sales offices are also available to help custom- ers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
PIC24HJ32GP202/204 and pic24hj16gp304 ds70289a-page 240 preliminary ? 2007 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds70289a PIC24HJ32GP202/204 and pic24hj16gp304 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2007 microchip technology inc. preliminary ds70289a-page 241 PIC24HJ32GP202/204 and pic24hj16gp304 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . architecture: 24 = 16-bit microcontroller flash memory family: hj = flash program memory, 3.3v product group: gp2 = general purpose family gp3 = general purpose family pin count: 02 = 28-pin 03 = 44-pin temperature range: i = -40 c to +85 c (industrial) e=-40 c to +125 c (extended) package: sp = skinny plastic dual in-line - 300 mil body (spdip) so = plastic small outline - wide - 7.5 mm body (soic) mm = plastic quad, no lead package - 6x6 mm body (qfn-s) pt = plastic thin quad flatpack - 10x10x1 mm body (tqfp ml = plastic quad, no lead package - 8x8 mm body (qfn) examples: a) PIC24HJ32GP202-e/sp: general-purpose pic24h, 32 kb program memory, 28-pin, extended temp., spdip package. microchip trademark architecture flash memory family program memory size (kb) product group pin count temperature range package pattern pic 24 hj 3 2 gp2 02 t e / sp - xxx tape and reel flag (if applicable)
ds70289a-page 242 preliminary ? 2007 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel: 60-4-646-8870 fax: 60-4-646-5086 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 06/25/07

▲Up To Search▲

Price & Availability of PIC24HJ32GP202

	To Download PIC24HJ32GP202 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .